Gate stack quality for gate-all-around field-effect transistors
View Patent ↗A semiconductor device includes a first gate-all-around field-effect transistor (GAA FET) device including a first gate stack having first channels, interfacial layers formed around the first channels, and dielectric material including first and second portions having respective thicknesses formed on the first interfacial layers. The semiconductor device further includes a second GAA FET device including a second gate stack having second channels, the interfacial layers formed around the second channels, and the dielectric material formed on the second interfacial layers. A threshold voltage (Vt) shift associated with the semiconductor device is achieved based on a thickness of the first portion of the dielectric material.
1. A method for fabricating a semiconductor device, comprising:
forming a first metal oxide layer on a first portion of dielectric material, the first portion of dielectric material being formed around first channels of a first gate stack of a first gate-all-around field-effect transistor (GAA FET) device and around second channels of a second gate stack of a second GAA FET device during a first deposition process; and
performing an anneal process after forming the first metal oxide layer to achieve a threshold voltage (Vt) shift based on a thickness of the first portion of the dielectric material.
2. The method of claim 1 , wherein the anneal process is performed below about 970 degrees Celsius.
3. The method of claim 1 , further comprising forming the first portion of dielectric material on interfacial layers, the interfacial layers being formed around the first and second channels during the first deposition process.
4. The method of claim 3 , further comprising performing a second anneal process after forming the first portion of the dielectric material.
5. The method of claim 4 , further comprising forming first and second sacrificial layers within the first and second gate stacks, respectively.
6. The method of claim 5 , further comprising forming a second metal oxide layer on each of the first and second sacrificial layers.
7. The method of claim 6 , further comprising forming a first protective layer on each of the first metal oxide layers, and removing the first protective layers and the first sacrificial layer along with the first metal oxide layer formed on the first sacrificial layer.
8. The method of claim 7 , further comprising, after forming the first metal oxide layer:
forming second protective layers on the second metal oxide layers; and
forming layers including amorphous silicon (a-Si) on the second protective layers.
9. The method of claim 1 , further comprising, after performing the anneal process:
removing all layers from the first GAA FET device and the second GAA FET device up to the first portion of the dielectric material; and
forming a second portion of the dielectric material on the first portion of the dielectric material during a second deposition process to complete the dielectric material formation on the interfacial layers.
10. The method of claim 9 , wherein the first and second portions of the dielectric material have a combined thickness between about 1 nm to about 3 nm.
11. The method of claim 10 , wherein the first portion of the dielectric material has a thickness between about 0.5 nm to about 2 nm and the second portion of the dielectric material has a thickness between about 0.5 nm and 1 nm.
12. The method of claim 9 , further comprising forming a work function metal within the first and second gate stacks after forming the second portion of the dielectric material.
13. A method for fabricating a semiconductor device, comprising:
forming a first portion of a dielectric material on interfacial layers during a first deposition process, the interfacial layers being formed around first channels of a first gate stack of a first gate-all-around field-effect transistor (GAA FET) device and around second channels of a second gate stack of a second GAA FET device;
performing a first anneal process after forming the first portion of the dielectric material;
forming first and second sacrificial layers within the first and second gate stacks, respectively;
forming a first metal oxide layer on each of the first and second sacrificial layers;
forming a first protective layer on each of the first metal oxide layers;
removing the first protective layers and first sacrificial layer along with the first metal oxide layer formed on the first sacrificial layer;
forming a second metal oxide layer on the first portion of the dielectric material of the first GAA FET device and on the first metal oxide layer of the second GAA FET device;
forming second protective layers on the second metal oxide layers;
forming layers including amorphous silicon (a-Si) on the second protective layers;
performing a second anneal process after forming the layers including a-Si to achieve a threshold voltage (Vt) shift based on a thickness of the first portion of the dielectric material;
removing all layers from the first GAA FET device and the second GAA FET device up to the first portion of the dielectric material; and
forming a second portion of the dielectric material on the first portion of the dielectric material during a second deposition process to complete the dielectric material formation on the interfacial layers.
14. The method of claim 13 , wherein the second anneal process is performed below about 970 degrees Celsius.
15. The method of claim 13 , wherein the first and second portions of the dielectric material have a combined thickness between about 1 nm to about 3 nm.
16. The method of claim 15 , wherein the first portion of the dielectric material has a thickness between about 0.5 nm to about 2 nm and the second portion of the dielectric material has a thickness between about 0.5 nm to about 1 mm.
17. The method of claim 13 , farther comprising forming a work function metal within the first and second gate stacks after forming the second portion of the dielectric material.