Testing fuse configurations in semiconductor devices
Methods, systems, and apparatus for testing semiconductor devices.
1. A semiconductor device comprising:
a soft-blow fuse circuit comprising a latch array and a fuse array, the latch array to receive fuse configuration data and to output a soft-blow signal based on the fuse configuration data, the soft-blow signal to configure the fuse array, the soft-blow fuse circuit to output a tune signal based on a configuration of blown fuses in the fuse array; and
a voltage regulator circuit coupled to the soft-blow fuse circuit, the voltage regulator circuit to receive the tune signal from the soft-blow fuse circuit and to generate a reference voltage having a value based on the tune signal.
2. The semiconductor device of claim 1 , wherein the soft-blow fuse circuit is operable in either a test mode or a normal operating mode.
3. The semiconductor device of claim 2 , wherein when operating in the test mode, the tune signal is based on data signals received by the soft-blow fuse circuit to simulate different configurations of blown fuses without any of the fuses in the fuse array being blow.
4. The semiconductor device of claim 3 , wherein when operating in the test mode, the soft-blow circuit is configured to generate the soft blow signal in response to the data signals and to generate the tune signal in response to the soft-blow signal.
5. The semiconductor device of claim 2 , wherein when operating in the normal operating mode, the tune signal is based on a current configuration of blown fuses in the fuse array.
6. The semiconductor device of claim 1 , wherein the voltage regulator circuit comprises:
a resistor chain to generate a plurality of different input voltages from a power source;
a multiplexer coupled to the resistor chain, the multiplexer to select one of the plurality of different input voltages based on the tune signal; and
an amplifier coupled to the multiplexer, the amplifier to generate the reference voltage based on the selected one of the plurality of different input voltages.
7. The semiconductor device of claim 1 , wherein the voltage regulator circuit is configured to receive a reset signal.
8. A method comprising:
receiving, by a soft-blow fuse circuit comprising a latch array and a fuse array, fuse configuration data,
generating, by the soft-blow fuse circuit, a soft-blow signal based on the fuse configuration data, the soft-blow signal to configure the fuse array;
generating, by the soft-blow fuse circuit, a tune signal based on a configuration of blown fuses in the fuse array; and
providing, by the soft-blow fuse circuit, the tune signal to a voltage regulator circuit coupled to the soft-blow fuse circuit, the voltage regulator circuit to generate a reference voltage having a value based on the tune signal.
9. The method device of claim 8 , wherein the soft-blow fuse circuit is operable in either a test mode or a normal operating mode.
10. The method device of claim 9 , wherein when operating in the test mode, generating the tune signal is based on data signals received by the soft-blow fuse circuit to simulate different configurations of blown fuses without any of the fuses in the fuse array being blow.
11. The method device of claim 10 , wherein when operating in the test mode, generating the soft blow signal is in response to the data signals and generating the tune signal is in response to the soft-blow signal.
12. The method device of claim 9 , wherein when operating in the normal operating mode, generating the tune signal is based on a current configuration of blown fuses in the fuse array.
13. The method device of claim 8 , wherein the voltage regulator circuit comprises:
a resistor chain to generate a plurality of different input voltages from a power source;
a multiplexer coupled to the resistor chain, the multiplexer to select one of the plurality of different input voltages based on the tune signal; and
an amplifier coupled to the multiplexer, the amplifier to generate the reference voltage based on the selected one of the plurality of different input voltages.
14. A system comprising:
a memory controller integrated circuit; and
a memory device integrated circuit, wherein the memory controller integrated circuit and the memory device integrated circuit are disposed within a single semiconductor device package, wherein the memory device integrated circuit comprises:
a soft-blow fuse circuit comprising a latch array and a fuse array, the latch array to receive fuse configuration data from the memory controller integrated circuit and to output a soft-blow signal based on the fuse configuration data, the soft-blow signal to configure the fuse array, the soft-blow fuse circuit to output a tune signal based on a configuration of blown fuses in the fuse array; and
a voltage regulator circuit coupled to the soft-blow fuse circuit, the voltage regulator circuit to receive the tune signal from the soft-blow fuse circuit and to generate a reference voltage having a value based on the tune signal.
15. The system of claim 14 , wherein the soft-blow fuse circuit is operable in either a test mode or a normal operating mode.
16. The system of claim 15 , wherein when operating in the test mode, the tune signal is based on data signals received by the soft-blow fuse circuit from the memory controller integrated circuit to simulate different configurations of blown fuses without any of the fuses in the fuse array being blow.
17. The system of claim 16 , wherein when operating in the test mode, the soft-blow circuit is configured to generate the soft blow signal in response to the data signals and to generate the tune signal in response to the soft-blow signal.
18. The system of claim 17 , wherein when operating in the normal operating mode, the tune signal is based on a current configuration of blown fuses in the fuse array.
19. The system of claim 14 , wherein the voltage regulator circuit comprises:
a resistor chain to generate a plurality of different input voltages from a power source;
a multiplexer coupled to the resistor chain, the multiplexer to select one of the plurality of different input voltages based on the tune signal; and
an amplifier coupled to the multiplexer, the amplifier to generate the reference voltage based on the selected one of the plurality of different input voltages.
20. The system of claim 14 , wherein the voltage regulator circuit is configured to receive a reset signal.