Semiconductor package structure and a method of manufacturing the same
A semiconductor package structure includes a substrate having a patterned surface, the patterned surface including a first region and a second region, wherein a first line width in the first region is smaller than a second line width in the second region. The semiconductor package structure further includes a first die hybrid-bonded to the first region through conductive features adapted for the first line width, and a second die bonded to the second region through conductive features adapted for the second line width. The manufacturing operations of the semiconductor package structure are also disclosed.
1. A semiconductor package structure, comprising:
a substrate having a patterned surface, the patterned surface comprising a first region and a second region, wherein a first line width in the first region is smaller than a second line width in the second region;
a first die hybrid-bonded to the first region through conductive features adapted for the first line width; and
a second die bonded to the second region through conductive features adapted for the second line width.
2. The semiconductor package structure of claim 1 , wherein the second die is flip-chip bonded to the second region.
3. The semiconductor package structure of claim 1 , wherein the second die is wire-bonded to the second region.
4. The semiconductor package structure of claim 1 , wherein the first line width is smaller than 20 micrometer.
5. The semiconductor package structure of claim 1 , wherein the second line width is greater than 20 micrometer.
6. The semiconductor package structure of claim 1 , wherein the substrate comprises a third die.
7. The semiconductor package structure of claim 6 , further comprising a through via on the patterned surface and disposed at a same level as the first die.
8. The semiconductor package structure of claim 1 , wherein the substrate comprises an interposer.
9. The semiconductor package structure of claim 8 , further comprising a through via in the interposer and below the patterned surface.
10. The semiconductor package structure of claim 1 , wherein the conductive features of the second die comprises solder bumps or metal wires.
11. A system-in-package (SIP) structure, comprising:
a substrate having a patterned surface, the patterned surface comprising a first conductive pattern and a second conductive pattern;
a first die hybrid-bonded to the first conductive pattern of the patterned surface through conductive features adapted for the first conductive pattern; and
a second die bonded to the second conductive pattern of the patterned surface through conductive features adapted for the second conductive pattern.
12. The SIP structure of claim 11 , wherein the patterned surface is a planarized surface.
13. The SIP structure of claim 11 , wherein the first conductive pattern has a first line width smaller than a second line width of the second conductive pattern.
14. The SIP structure of claim 11 , wherein the first conductive pattern has a line width smaller than 20 micrometers, and the second conductive pattern having a line width greater than 20 micrometers.
15. A method for manufacturing a semiconductor package structure, comprising:
providing a substrate having a patterned surface, the patterned surface comprising a first conductive pattern and a second conductive pattern,
performing a planarization operation on the patterned surface, the first conductive pattern having a first dishing response to a planarization operation, and the second conductive pattern having a second dishing response to the planarization operation, the first dishing response being different from the second dishing response;
hybrid-bonding a first die to the first region through conductive features adapted for the first conductive pattern; and
bonding a second die to the first region through conductive features adapted for the second conductive pattern.
16. The method of claim 15 , wherein performing the planarization operation comprises:
performing a chemical mechanical polishing operation prior to hybrid-bonding the first die to the first region.
17. The method of claim 15 , wherein the conductive feature of the first die comprises copper pillars.
18. The method of claim 17 , wherein the conductive feature of the second die comprises solder bump or metal wires.
19. The method of claim 15 , wherein providing the substrate having the patterned surface comprises:
providing a third die;
forming a conductive layer over a surface of the third die; and
forming the first conductive pattern and the second conductive pattern in the conductive layer.
20. The method of claim 15 , wherein providing the substrate having the patterned surface comprises:
providing an interposer having the patterned surface and a through via in the interposer electrically connected to the patterned surface.