Parasitic channel mitigation using silicon carbide diffusion barrier regions
View Patent ↗III-nitride materials are generally described herein, including material structures comprising III-nitride material regions and silicon-containing substrates. Certain embodiments are related to gallium nitride materials and material structures comprising gallium nitride material regions and silicon-containing substrates.
1. A semiconductor structure, comprising:
a substrate comprising silicon and comprising at least a layer having a resistivity of greater than 10 2 Ohms-cm;
a diffusion barrier region comprising an epitaxial layer of silicon carbide (SiC) located over a surface of the substrate, the epitaxial layer of SiC comprising a vanadium dopant and having a resistivity of greater than 1000 Ohms-cm; and
a III-nitride material region located over the diffusion barrier region, wherein a surface region of the substrate comprises a low-conductivity parasitic channel having a total integrated surface region charge of less than about 10 12 /cm 2 .
2. The semiconductor structure of claim 1 , wherein a peak of a sum of concentrations of Group III species in the substrate is less than about 10 17 /cm 3 .
3. The semiconductor structure of claim 1 , wherein a peak of a sum of concentrations of Al, Ga, and In in the substrate is less than about 10 17 /cm 3 .
4. The semiconductor structure of claim 1 , wherein a peak concentration of at least one of Al, Ga, or In in the substrate is less than about 10 17 /cm 3 .
5. The semiconductor structure of claim 1 , wherein the low-conductivity parasitic channel has a peak free carrier concentration that is less than about 10 17 /cm 3 .
6. The semiconductor structure of claim 1 , wherein the substrate is a silicon substrate.
7. The semiconductor structure of claim 1 , wherein the substrate is a bulk silicon wafer.
8. The semiconductor structure of claim 1 , wherein the substrate is a silicon-on-insulator substrate.
9. The semiconductor structure of claim 1 , wherein a transistor is formed over the surface of the substrate.
10. The semiconductor structure of claim 1 , wherein the III-nitride material region comprises GaN.
11. The semiconductor structure of claim 1 , wherein the III-nitride material region comprises a III-nitride nucleation layer.
12. The semiconductor structure of claim 1 , wherein the III-nitride material region comprises a III-nitride transition layer.
13. The semiconductor structure of claim 1 , wherein:
the III-nitride material region comprises a III-nitride transition layer; and
the III-nitride transition layer is compositionally graded.
14. The semiconductor structure of claim 1 , wherein the III-nitride material region comprises a III-nitride buffer layer.
15. The semiconductor structure of claim 1 , wherein the III-nitride material region comprises a III-nitride device region.
16. The semiconductor structure of claim 1 , further comprising a second barrier region located between the III-nitride material region and the substrate.
17. The semiconductor structure of claim 1 , further comprising:
a second diffusion barrier region located between the III-nitride material region and the substrate, wherein the second diffusion barrier region comprises at least one of an AlN region, a rare-earth oxide region, a rare-earth nitride region, or an elemental diboride region.
18. The semiconductor structure of claim 1 , wherein the substrate comprises an active species coupled to an external species or capable of reacting with an external species.
19. The semiconductor structure of claim 1 , wherein the diffusion barrier region has a thickness of greater than about 0.1 micron.
20. The semiconductor structure of claim 1 , wherein the diffusion barrier region has a thickness of greater than about 1 micron.
21. The semiconductor structure of claim 1 , wherein the diffusion barrier region comprises 3C—SiC.
22. The semiconductor structure of claim 1 , wherein the diffusion barrier region comprises a carbonized layer formed on a top surface of the substrate and the epitaxial layer of SiC formed over the carbonized layer.
23. The semiconductor structure of claim 22 , wherein the carbonized layer is formed by contact of a top surface of the substrate with carbon or a carbon species.
24. The semiconductor structure of claim 1 , wherein the diffusion barrier region comprises a plurality of epitaxial layers each formed using different growth techniques.
25. The semiconductor structure of claim 1 , wherein the diffusion barrier region comprises an epitaxial layer of 3C—SiC, 4H—SiC, or 6H—SiC.
26. The semiconductor structure of claim 1 , wherein the epitaxial layer of SiC is doped to increase resistivity.
27. A method of manufacturing a semiconductor structure, comprising:
providing a substrate comprising silicon and comprising at least a layer having a resistivity of greater than 10 2 Ohms-cm;
forming a diffusion barrier region comprising an epitaxial layer of silicon carbide (SiC) located over a surface of the substrate, the epitaxial layer of SiC comprising a vanadium dopant and having a resistivity of greater than 1000 Ohms-cm; and
forming a III-nitride material region located over the diffusion barrier region, wherein a surface region of the substrate comprises a low-conductivity parasitic channel having a total integrated surface region charge of less than about 10 12 /cm 2 .
28. The method of claim 27 , wherein forming the diffusion barrier region comprises:
contacting the surface of the substrate with carbon to form a carbonized layer; and
growing the epitaxial layer of SiC over the carbonized layer.