Method of manufacturing a semiconductor device and a semiconductor device
In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers containing Ge and second semiconductor layers are alternately stacked, is formed over a bottom fin structure. A Ge concentration in the first semiconductor layers is increased. A sacrificial gate structure is formed over the fin structure. A source/drain epitaxial layer is formed over a source/drain region of the fin structure. The sacrificial gate structure is removed. The second semiconductor layers in a channel region are removed, thereby releasing the first semiconductor layers in which the Ge concentration is increased. A gate structure is formed around the first semiconductor layers in which the Ge concentration is increased.
1. A method of manufacturing a semiconductor device, comprising:
forming a fin structure in which first semiconductor layers containing Ge and second semiconductor layers are alternately stacked over a bottom fin structure;
increasing a Ge concentration in the first semiconductor layers;
after the Ge concentration is increased, forming a sacrificial gate structure over the fin structure;
after the sacrificial gate structure is formed, forming a source/drain epitaxial layer over a source/drain region of the fin structure;
after the source/drain epitaxial layer is formed, removing the sacrificial gate structure;
after the sacrificial gate structure is removed, removing the second semiconductor layers in a channel region, thereby releasing the first semiconductor layers in which the Ge concentration is increased; and
forming a gate structure around the first semiconductor layers in which the Ge concentration is increased.
2. The method of claim 1 , wherein the Ge concentration is increased by oxidizing the first semiconductor layers.
3. The method of claim 2 , wherein the Ge concentration is increased by:
forming an oxide layer over the fin structure; and
performing a thermal treatment, thereby oxidizing the first semiconductor layers.
4. The method of claim 3 , wherein the thermal treatment is performed at 800° C. to 1000° C.
5. The method of claim 3 , wherein after the thermal treatment, the oxide layer is removed.
6. The method of claim 5 , wherein the forming the oxide layer, the performing the thermal treatment and the removing the oxide layer are repeated.
7. The method of claim 1 , wherein:
the first semiconductor layer is made of SiGe, and
the Ge concentration of the first semiconductor layers after the Ge concentration is increased is in a range from 45 atomic % to 55 atomic %.
8. The method of claim 7 , wherein:
the second semiconductor layer is made of Si, and
the Ge concentration of the first semiconductor layers before the Ge concentration is increased is in a range from 35 atomic % to 45 atomic %.
9. The method of claim 1 , wherein when the sacrificial gate structure is formed over the fin structure, a width of the first semiconductor layers is smaller than a width of the second semiconductor layers.
10. The method of claim 1 , wherein when the sacrificial gate structure is formed over the fin structure, a width of the first semiconductor layers is smaller than a thickness of the first semiconductor layers.
11. A method of manufacturing a semiconductor device, comprising:
forming a first fin structure and a second fin structure, in each of which first semiconductor layers containing Ge and second semiconductor layers are alternately stacked over a bottom fin structure;
increasing a Ge concentration in the first semiconductor layers of the second fin structure, while protecting the first fin structure;
after the Ge concentration is increased, forming a sacrificial gate structure over the first and second fin structures;
after the sacrificial gate structure is formed, forming a first source/drain epitaxial layer over a source/drain region of the first fin structure;
forming a second source/drain epitaxial layer over a source/drain region of the second fin structure;
after the first and second source/drain epitaxial layers are formed, removing the sacrificial gate structure;
after the sacrificial gate structure is removed, removing the first semiconductor layers in a channel region of the first fin structure, thereby releasing the second semiconductor layers;
removing the second semiconductor layers in a channel region of the second fin structure, thereby releasing the first semiconductor layers in which the Ge concentration is increased; and
forming a gate structure around the released first semiconductor layers and the released second semiconductor layers.
12. The method of claim 11 , wherein the Ge concentration is increased by oxidizing the first semiconductor layers.
13. The method of claim 12 , wherein the Ge concentration is increased by:
forming an oxide layer over the second fin structure; and
performing a thermal treatment, thereby oxidizing the first semiconductor layers.
14. The method of claim 13 , wherein the thermal treatment is performed at 800° C. to 1000° C.
15. The method of claim 13 , wherein after the thermal treatment, the oxide layer is removed.
16. The method of claim 15 , wherein the forming the oxide layer, the performing the thermal treatment and the removing the oxide layer are repeated.
17. The method of claim 11 , wherein:
the first semiconductor layer is made of SiGe, and
the Ge concentration of the first semiconductor layers after the Ge concentration is increased is in a range from 45 atomic % to 55 atomic %.
18. The method of claim 17 , wherein:
the second semiconductor layer is made of Si, and
the Ge concentration of the first semiconductor layers before the Ge concentration is increased is in a range from 35 atomic % to 45 atomic %.
19. A method of manufacturing a semiconductor device, comprising:
forming a first fin structure and a second fin structure, in each of which first semiconductor layers containing Ge and second semiconductor layers are alternately stacked over a bottom fin structure;
increasing an Ge concentration in the first semiconductor layers of the second fin structure, while protecting the first fin structure;
after the Ge concentration is increased, forming a sacrificial gate structure over the first and second fin structures;
after the sacrificial gate structure is formed, forming a first source/drain epitaxial layer over a source/drain region of the first fin structure;
forming a second source/drain epitaxial layer over a source/drain region of the second fin structure;
after the first and second source/drain epitaxial layers are formed, removing the sacrificial gate structure;
after the sacrificial gate structure is removed, removing the first semiconductor layers in a channel region of the first fin structure, thereby releasing the second semiconductor layers;
removing the second semiconductor layers in a channel region of the second fin structure, thereby releasing the first semiconductor layers in which the Ge concentration is increased; and
forming a first gate structure around the released first semiconductor layers and a second gate structure around the released second semiconductor layers.
20. The method of claim 19 , wherein the Ge concentration is increased by oxidizing the first semiconductor layers.