Semiconductor device and method for manufacturing same
According to one embodiment, a source layer includes a semiconductor layer including an impurity. A stacked body includes a plurality of electrode layers stacked with an insulator interposed. A gate layer is provided between the source layer and the stacked body. The gate layer is thicker than a thickness of one layer of the electrode layers. A semiconductor body extends in a stacking direction of the stacked body through the stacked body and the gate layer. The semiconductor body further extends in the semiconductor layer where a side wall portion of the semiconductor body contacts the semiconductor layer. The semiconductor body does not contact the electrode layers and the gate layer.
1. A semiconductor device, comprising:
a substrate including a control circuit, the control circuit provided at a surface of the substrate;
a source layer including a semiconductor layer provided above the control circuit and including an impurity;
a stacked body provided above the source layer, the stacked body including a plurality of electrode layers stacked with an insulator interposed;
a gate layer provided between the source layer and the stacked body, the gate layer being thicker than a thickness of one layer of the electrode layers;
a semiconductor body extending in a stacking direction of the stacked body through the stacked body and the gate layer, the semiconductor body further extending in the semiconductor layer where a side wall portion of the semiconductor body contacts the semiconductor layer, the semiconductor body not contacting the electrode layers and the gate layer; and
a charge storage portion provided between the semiconductor body and one of the electrode layers,
wherein an impurity concentration of the side wall portion of the semiconductor body is higher than another impurity concentration of a portion of the semiconductor body opposing the stacked body.
2. The semiconductor device according to claim 1 , wherein a distance between the side wall portion and a portion of the semiconductor body opposing the gate layer is less than a thickness of the gate layer.
3. The semiconductor device according to claim 1 , wherein an impurity concentration of a portion of the semiconductor body opposing the gate layer is higher than another impurity concentration of a portion of the semiconductor body opposing the stacked body.
4. The semiconductor device according to claim 1 , wherein
the electrode layers include:
a drain-side selection gate thinner than the gate layer, the drain-side selection gate being at least one layer;
a source-side selection gate provided between the drain-side selection gate and the gate layer, the source-side selection gate being at least one layer and being thinner than the gate layer; and
a plurality of cell gates opposing the charge storage portion and being provided between the drain-side selection gate and the source-side selection gate, the plurality of cell gates each being thinner than the gate layer.
5. The semiconductor device according to claim 1 , wherein the gate layer is a silicon layer including phosphorus.
6. The semiconductor device according to claim 1 , wherein the semiconductor layer is a silicon layer including phosphorus.
7. The semiconductor device according to claim 1 , wherein
the source layer further includes a layer including a metal, and
the semiconductor layer is provided between the gate layer and the layer including the metal.
8. The semiconductor device according to claim 1 , wherein the charge storage portion is continuous in the stacking direction between the stacked body and the semiconductor body.
9. The semiconductor device according to claim 8 , wherein an insulating film is provided between the gate layer and the semiconductor body, the insulating film including the same type of film as the charge storage portion.
10. The semiconductor device according to claim 8 , wherein an insulating film is provided under a bottom surface of the semiconductor body, the insulating film including the same type of film as the charge storage portion.
11. The semiconductor device according to claim 1 , wherein
the semiconductor layer includes:
a first semiconductor layer;
a second semiconductor layer provided between the first semiconductor layer and the gate layer; and
a third semiconductor layer provided along an upper surface of the first semiconductor layer, a lower surface of the second semiconductor layer, and the side wall portion of the semiconductor body, and
an air gap is formed between the third semiconductor layer provided on the upper surface of the first semiconductor layer and the third semiconductor layer provided on the lower surface of the second semiconductor layer.
12. The semiconductor device according to claim 1 , wherein the source layer is provided between the substrate and the gate layer, the semiconductor layer of the source layer contacts the substrate.
13. The semiconductor device according to claim 12 , wherein
the substrate includes
an n-type semiconductor region contacting the semiconductor layer of the source layer, and
a p-type semiconductor region, the n-type semiconductor region and the p-type semiconductor region forming a p-n junction.
14. The semiconductor device according to claim 12 , wherein the semiconductor body pierces the source layer, and a lower end portion of the semiconductor body reaches the substrate.
15. The semiconductor device according to claim 12 , further comprising
a plug provided between the source layer and a peripheral portion of the gate layer, the plug connecting the source layer and the peripheral portion of the gate layer, and
a separation portion separating the gate layer into the peripheral portion and a cell portion.