Content addressable memory device having electrically floating body transistor
A content addressable memory cell includes a first floating body transistor and a second floating body transistor. The first floating body transistor and the second floating body transistor are electrically connected in series through a common node. The first floating body transistor and the second floating body transistor store complementary data.
1. A content addressable memory cell comprising:
a first floating body transistor;
a second floating body transistor;
a third transistor; and
a fourth transistor;
wherein said first floating body transistor is connected to a gate of said third transistor; and
wherein said second floating body transistor is connected to a gate of said fourth transistor.
2. The content addressable memory cell of claim 1 , wherein said first floating body transistor and said second floating body transistor store complementary data.
3. The content addressable memory cell of claim 1 , wherein said first floating body transistor and said second floating body transistor store the same data.
4. The content addressable memory cell of claim 1 , wherein said third and fourth transistors are connected in parallel.
5. The content addressable memory cell of claim 1 , wherein said third and fourth transistors are connected in series.
6. The content addressable memory cell of claim 1 , wherein said content addressable memory cell may function as binary content addressable memory cell or ternary content addressable memory cell.
7. The content addressable memory cell of claim 1 , wherein said first floating body transistor and said second floating body transistor comprise a buried well region.
8. The content addressable memory cell of claim 1 , wherein said first floating body transistor and said second floating body transistor comprise a buried insulator region.
9. The content addressable memory cell of claim 1 , further comprising a third floating body transistor.
10. A content addressable memory cell comprising:
a first bipolar device having a first floating base region, a first collector, and a first emitter;
a second bipolar device having a second floating base region, a second collector, and a second emitter;
a third transistor; and
a fourth transistor;
wherein said first bipolar device is connected to a gate of said third transistor; and
wherein said second bipolar device is connected to a gate of said fourth transistor.
11. The content addressable memory cell of claim 10 , wherein said first bipolar device and said second bipolar device store complementary data.
12. The content addressable memory cell of claim 10 , wherein said first bipolar device and said second bipolar device store the same data.
13. The content addressable memory cell of claim 10 , wherein said third and fourth transistors are connected in parallel.
14. The content addressable memory cell of claim 10 , wherein said third and fourth transistors are connected in series.
15. The content addressable memory cell of claim 10 , wherein said content addressable memory cell may function as binary content addressable memory cell or ternary content addressable memory cell.
16. The content addressable memory cell of claim 10 , wherein said first bipolar device and said second bipolar device comprise a buried well region.
17. The content addressable memory cell of claim 10 , wherein said first bipolar device and said second bipolar device comprise a buried insulator region.
18. The content addressable memory cell of claim 10 , further comprising a third bipolar device having a third floating base region, a third collector, and a third emitter.