IP Library › Granted Patent US 11,282,791
Granted Patent B2
US 11,282,791 · App. 16/454,086 · Granted Mar 22, 2022

Semiconductor device having a heat dissipation structure connected chip package

Inventors: Po-Yuan Teng (Hsinchu, TW); Hung-Yi Kuo (Taipei, TW); Hao-Yi Tsai (Hsinchu, TW); Tin-Hao Kuo (Hsinchu, TW); Yu-Chia Lai (Miaoli County, TW); Shih-Wei Chen (Hsinchu, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H01L23/5382H01L21/485H01L21/4853H01L21/4857H01L21/4882H01L21/563H01L23/3157H01L23/473H01L23/5383H01L23/5386H01L23/367H01L25/0657H01L25/074H01L25/0756H01L25/117H01L2225/1011
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Quick Facts
Patent No.
US 11,282,791
App. No.
16/454,086
Granted
Mar 22, 2022
Kind
B2
Abstract

A semiconductor device includes a first chip package, a heat dissipation structure and an adapter. The first chip package includes a semiconductor die laterally encapsulated by an insulating encapsulant, the semiconductor die has an active surface and a back surface opposite to the active surface. The heat dissipation structure is connected to the chip package. The adapter is disposed over the first chip package and electrically connected to the semiconductor die.

Claims (30)

1. A semiconductor device, comprising:

a first chip package comprising a semiconductor die laterally encapsulated by an insulating encapsulant, the semiconductor die having an active surface and a back surface opposite to the active surface;

a heat dissipation structure connected to the first chip package; and

an adapter disposed over the first chip package and electrically connected to the semiconductor die.

2. The semiconductor device as claimed in claim 1 , wherein the first chip package further comprises a redistribution circuit structure disposed over the active surface of the semiconductor die and the insulating encapsulant, and the redistribution circuit structure electrically connects the adapter to the semiconductor die.

3. The semiconductor device as claimed in claim 1 , further comprising a second chip package mounted on the adapter and electrically connected to the adapter.

4. The semiconductor device as claimed in claim 3 , wherein a top surface of the adapter comprises a plurality of insertion holes and a plurality of terminals disposed in the plurality of insertion holes, and the second chip package is connected to the adapter through the plurality of insertion holes.

5. The semiconductor device as claimed in claim 3 , wherein the second chip package is physically and electrically connected to the adapter through solder.

6. The semiconductor device as claimed in claim 1 , wherein the adapter comprises a circuit board and a plurality of sockets formed on the circuit board.

7. The semiconductor device as claimed in claim 1 , wherein the heat dissipation structure comprises a heat spreader having a flow channel for a cooling liquid, the back surface of the semiconductor die comprises a thermal enhancement pattern, and the cooling liquid in the flow channel being in contact with the thermal enhancement pattern.

8. The semiconductor device as claimed in claim 7 , wherein the thermal enhancement pattern comprises a recess, and a cooling liquid that flows in the flow channel contacts the recess.

9. A semiconductor device, comprising:

a chip package comprising a semiconductor die laterally encapsulated by an insulating encapsulant, the semiconductor die having an active surface, a back surface opposite to the active surface, and a thermal enhancement pattern on the back surface;

a heat dissipation structure connected to the chip package, the heat dissipation structure comprising a heat spreader having a flow channel for a cooling liquid, and the cooling liquid in the flow channel being in contact with the thermal enhancement pattern; and

an adapter disposed over the chip package and electrically connected to the semiconductor die.

10. The semiconductor device as claimed in claim 9 , wherein the thermal enhancement pattern comprises a recess distributed on the back surface of the semiconductor die.

11. The semiconductor device as claimed in claim 10 , further comprising a thermal conductive material on the back surface of the semiconductor die and covering the recess.

12. The semiconductor device as claimed in claim 9 , wherein the thermal enhancement pattern comprises a recessed region and a plurality of heat dissipation fins in the recessed region, the plurality of heat dissipation fins protrudes from a bottom of the recessed region toward the heat dissipation structure.

13. The semiconductor device as claimed in claim 12 , wherein the plurality of heat dissipation fins comprises a first heat dissipation fin and a second heat dissipation fin, the first heat dissipation fin and the second heat dissipation fin define a meandering flow channel.

14. The semiconductor device as claimed in claim 9 , wherein the thermal enhancement pattern comprises a recessed region and a plurality of heat dissipation pillars in the recessed region, the plurality of heat dissipation pillars protrudes from a bottom of the recessed region toward the heat dissipation structure.

15. The semiconductor device as claimed in claim 9 , further comprising a redistribution circuit structure disposed between the adapter and the active surface of the semiconductor die to electrically connect the adapter to the semiconductor die.

16. The semiconductor device as claimed in claim 9 , wherein the heat spreader further comprises an inlet and an outlet, and the flow channel is communicated between the inlet and the outlet.

17. A semiconductor device, comprising:

a first chip package comprising a semiconductor die, an insulating encapsulant laterally encapsulating the semiconductor dies, and a redistribution circuit structure disposed over the semiconductor die and the insulating encapsulant;

a heat dissipation structure connected to the first chip package;

an adapter disposed over the first chip package, wherein the adapter is electrically connected to the semiconductor die through the redistribution circuit structure; and

a second chip package mounted on the adapter and electrically connected to the first chip package through the adapter and the redistribution circuit structure.

18. The semiconductor device as claimed in claim 17 , wherein a top surface of the adapter comprises a plurality of insertion holes and a plurality of terminals disposed in the plurality of insertion holes, and the second chip package is connected to the adapter through the plurality of terminals of the adapter.

19. The semiconductor device as claimed in claim 17 , wherein the second chip package is physically and electrically connected to the adapter through solder.

20. The semiconductor device as claimed in claim 17 , wherein the heat dissipation structure comprises a heat spreader having a flow channel for a cooling liquid, the back surface of the semiconductor die comprises a thermal enhancement pattern, and the cooling liquid in the flow channel being in contact with the thermal enhancement pattern.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 4, 2019
From: TENG, PO-YUAN; KUO, HUNG-YI; TSAI, HAO-YI; KUO, TIN-HAO; LAI, YU-CHIA; CHEN, SHIH-WEI
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 050253/0750 →
Continuity (1)
Related Publication 20200411439A1 · Dec 31, 2020