Integrated electrical/optical interface with two-tiered packaging
An improved chip package, and methods for fabricating the same are provided that utilize two tier packaging of an optical die and another die commonly disposed over a substrate. In one example, a chip package is provided that includes an optical die, a core die, and an electrical/optical interface die are all disposed over a common substrate. In one example, a first routing region is provided between the core and electrical/optical interface dies, a second routing region is provided between the electrical/optical interface die and the optical dies, and a third routing region is disposed between the substrate and the core and electrical/optical interface dies.
1. A chip package comprising:
a package substrate having a top surface;
a first integrated circuit (IC) die mounted above the top surface of the package substrate;
a second IC die mounted above top surface of the package substrate;
an optical die mounted in a notch formed in the top surface of the package substrate; and
an interposer disposed between the package substrate and the first IC die, the interposer disposed between the package substrate and the second IC die, the interposer disposed between the second IC die and the optical die, the interposer having a first surface and a second surface opposite the first surface, the interposer comprising:
a plurality of first group of routings extending beneath the first surface of the interposer coupling the optical die to the second IC die;
a plurality of second group of routings extending beneath the first surface of the interposer coupling the first IC die and a bottom surface of the interposer; and
a plurality of third group of routings extending beneath the first surface of the interposer coupling the first IC die to the first group of routings of the second IC die.
2. The chip package of claim 1 , wherein a density of the third group of routings is greater than a density of the second group of routings.
3. The chip package of claim 1 , wherein a density of the third group of routings is at least twice a density of the second group of routings.
4. The chip package of claim 1 , wherein the third group of routings are configured to transmit signals at a rate slower than signals transmitted on the second group of routings.
5. The chip package of claim 4 , wherein the rate that third group of routings are configured to transmit signals is between about 5 Gbps and about 10 Gbps.
6. The chip package of claim 4 , wherein the first IC die comprises circuitry having transmitter circuitry configured to transmit a plurality of data signals and a circuitry configured to transmit a clock signal.
7. The chip package of claim 6 , wherein the second IC die comprises receiver circuitry configured to sample the data signals transmitted by a driver circuitry using the clock signal transmitted by a clock driver.
8. The chip package of claim 7 , wherein the receiver circuitry of the second IC die does not include clock recovery circuitry.
9. The chip package of claim 1 , wherein the optical die is disposed under a portion of the second IC die.
10. The chip package of claim 1 , wherein a portion of a top surface of the optical die is not covered by the interposer.
11. The chip package of claim 1 , wherein a density of the third group of routings is greater than a density of routings in the package substrate.
12. A chip package comprising:
a package substrate having a built-up layer disposed on a core substrate, the built-up layer forming a top surface of the package substrate, a portion of the core substrate exposed to form a notch in the top surface of the package substrate;
an interposer disposed on the package substrate;
a first integrated circuit (IC) die mounted on a top surface of the interposer, the first IC die comprising circuitry the first IC die comprises circuitry configured to transmit a plurality of data signals and to transmit a clock signal;
a second IC die mounted on the top surface of the interposer, the second IC die comprising circuitry configured to receive the data signals transmitted by the first IC die using the clock signal transmitted by the first IC die; and
an optical die mounted in the notch formed in the top surface of the package substrate, the optical die is disposed under a portion of the second IC die; wherein the interposer is disposed between the package substrate and the first IC die, the interposer is disposed between the package substrate and the second IC die, the interposer is disposed between the second IC die and the optical die, the interposer having a first surface and a second surface opposite the first surface, the interposer comprising:
a plurality of first group of routings extending beneath the first surface of the interposer coupling the optical die to the second IC die;
a plurality of second group of routings extending beneath the first surface of the interposer coupling the first IC die and a bottom surface of the package substrate; and
a plurality of third group of routings disposed through the interposer and coupling a driver circuitry to the circuitry of the second die, the plurality of third group of routings having a routing density that is greater than a routing density of the plurality of first group of routings, the third group of routings configured to transmit signals at a rate slower than signals transmitted on the first group of routings while having a throughput density of at least 2 Tbps/mm and an energy efficiency of less than 1 pJ/bit.
13. The chip package of claim 12 , wherein a portion of a top surface of the optical die not covered by the interposer.
14. The chip package of claim 12 further comprising:
an optical connector coupled to a side or a top surface of the optical die that is not covered by the interposer.