IP Library › Granted Patent US 12,283,585
Granted Patent B2
US 12,283,585 · App. 18/434,703 · Granted Apr 22, 2025

Optoelectronic device package and method of manufacturing the same

Inventor: Chi-Han Chen (Taoyuan, TW)
Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
H01L25/167H01L21/4853H01L21/4857H01L21/565H01L21/568H01L21/6835H01L23/3128H01L23/5383H01L23/5386H01L23/5389H01L24/19H01L24/20H01L2221/68372H01L2224/214
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,283,585
App. No.
18/434,703
Granted
Apr 22, 2025
Kind
B2
Abstract

An optoelectronic device package includes a first redistribution layer (RDL), a first electronic die disposed over the first RDL, wherein an active surface of the first electronic die faces the first RDL. The optoelectronic device package further includes a second electronic die disposed over the first RDL, and a photonic die disposed over and electrically connected to the second electronic die. An active surface of the second electronic die is opposite to the first RDL.

Claims (40)

1. An optoelectronic device package, comprising:

a first redistribution layer (RDL);

a processing die disposed over the first RDL;

a first electronic component disposed over the first RDL and electrically connected to the processing die through the first RDL;

a second electronic component disposed over the first RDL,

wherein the first electronic component is disposed between the processing die and the second electronic component, and an edge of the first RDL protrudes out of an outer edge of the second electronic component in a direction away from the first electronic component; and

a photonic die disposed over the second electronic component, wherein a level of an upper surface of the photonic die is higher than a level of an upper surface of the processing die with respect to the first RDL.

2. The optoelectronic device package of claim 1 , wherein a technology node of the processing die is less than that of the first electronic component.

3. The optoelectronic device package of claim 1 , further comprising:

an encapsulation layer encapsulating the first electronic component and the second electronic component, wherein the encapsulation layer is spaced apart from the processing die.

4. The optoelectronic device package of claim 3 , wherein the edge of first RDL protrudes out of an edge of the encapsulation layer in the direction away from the first electronic component.

5. The optoelectronic device package of claim 1 , wherein the processing die has an active surface, the second electronic component has an active surface, and the active surface of the processing die is closer to the first RDL than to the active surface of the second electronic component.

6. The optoelectronic device package of claim 1 , further comprising: a lid disposed over the processing die by a thermal interface material.

7. The optoelectronic device package of claim 1 , further comprising: a protective layer disposed between the processing die and the first RDL.

8. An optoelectronic device package, comprising:

a first redistribution layer (RDL);

a first electronic die disposed over the first RDL and having an active surface;

a second electronic die disposed over the first RDL and having an active surface;

a photonic die disposed adjacent to the second electronic die;

a second RDL under the first electronic die and the second electronic die, wherein the second RDL is connected to the active surface of the first electronic die;

a third RDL over the first electronic die and the second electronic die, wherein the third RDL is electrically connected to the active surface of the second electronic die; and

an underfill layer disposed between the photonic die and the third RDL.

9. The optoelectronic device package of claim 8 , wherein the photonic die is disposed over and electrically connected to the second electronic die.

10. The optoelectronic device package of claim 9 , wherein the photonic die is electrically connected to the first electronic die and the second electronic die through the third RDL.

11. The optoelectronic device package of claim 10 , wherein the photonic die overhangs the third RDL.

12. The optoelectronic device package of claim 8 , further comprising:

an encapsulation layer encapsulating the first electronic die and the second electronic die, wherein the encapsulation layer is disposed between the first RDL and the third RDL.

13. The optoelectronic device package of claim 12 , further comprising:

a conductive via passing the encapsulation layer and electrically connecting the first RDL and the third RDL.

14. The optoelectronic device package of claim 8 , wherein the photonic die is configured to be optically coupled to an optical component.

15. The optoelectronic device package of claim 14 , wherein at least a portion of the optical component is disposed under the photonic die.

16. An optoelectronic device package, comprising:

a first redistribution layer (RDL);

a processing die disposed over the first RDL and having an active surface;

a first electronic component disposed over the first RDL and having an active surface; and

a second electronic component disposed over the first RDL and having an active surface and an opposing surface,

wherein the opposing surface of the second electronic component, the active surface of the processing die and the active surface of the first electronic component are misaligned with each other,

and wherein each of an elevation of the opposing surface of the second electronic component and an elevation of the active surface of the first electronic component is higher than an elevation of the active surface of the processing die with respect to the first RDL.

17. The optoelectronic device package of claim 16 , further comprising:

a second RDL disposed between the second electronic component and the first RDL, wherein the second RDL overlaps the processing die along a horizontal direction.

Continuity (2)
Continuation 17319948 · May 13, 2021
Related Publication 20240213233A1 · Jun 27, 2024
References Cited (18)
US 8971676B1 · Thacker et al. · 2015 [cited by applicant]
US 9153461B2 · Henderson et al. · 2015 [cited by applicant]
US 9432121B2 · Lesea et al. · 2016 [cited by applicant]
US 11107770B1 · Ramalingam et al. · 2021 [cited by applicant]
US 11536897B1 · Thompson et al. · 2022 [cited by applicant]
US 20160216445A1 · Thacker et al. · 2016 [cited by applicant]
US 20160260684A1 · Zhai · 2016 [cited by examiner]
US 20170309606A1 · Lee · 2017 [cited by examiner]
US 20180102470A1 · Das · 2018 [cited by examiner]
US 20180145049A1 · Lin · 2018 [cited by examiner]
US 20180188448A1 · Yim · 2018 [cited by examiner]
US 20180350751A1 · Sun · 2018 [cited by examiner]
US 20190041594A1 · Li et al. · 2019 [cited by applicant]
US 20190137706A1 · Xie · 2019 [cited by applicant]
US 20190244905A1 · Yu · 2019 [cited by examiner]
US 20190317287A1 · Raghunathan et al. · 2019 [cited by applicant]
Non-Final Office Action for U.S. Appl. No. 17/319,948, issued Apr. 5, 2023, 15 pages. [cited by applicant]
Notice of Allowance for U.S. Appl. No. 17/319,948, issued Sep. 27, 2023, 10 pages. [cited by applicant]