IP Library › Granted Patent US 11,024,593
Granted Patent B2
US 11,024,593 · App. 16/458,719 · Granted Jun 1, 2021

Metal bumps and method forming same

Inventors: Ming-Da Cheng (Jhubei, TW); Yung-Ching Chao (Gukeng Township, TW); Chun Kai Tzeng (Tainan, TW); Cheng Jen Lin (Kaohsiung, TW); Chin Wei Kang (Tainan, TW); Yu-Feng Chen (Hsinchu, TW); Mirng-Ji Lii (Sinpu Township, TW)
Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
H01L24/11H01L23/3192H01L23/5226H01L24/08H01L24/13H01L24/16H01L24/32H01L23/488H01L24/03H01L24/05H01L2224/0401H01L2224/32501
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Quick Facts
Patent No.
US 11,024,593
App. No.
16/458,719
Granted
Jun 1, 2021
Kind
B2
Abstract

A method of forming an integrated circuit structure includes forming a patterned passivation layer over a metal pad, with a top surface of the metal pad revealed through a first opening in the patterned passivation layer, and applying a polymer layer over the patterned passivation layer. The polymer layer is substantially free from N-Methyl-2-pyrrolidone (NMP), and comprises aliphatic amide as a solvent. The method further includes performing a light-exposure process on the polymer layer, performing a development process on the polymer layer to form a second opening in the polymer layer, wherein the top surface of the metal pad is revealed to the second opening, baking the polymer, and forming a conductive region having a via portion extending into the second opening.

Claims (41)

1. A method of forming an integrated circuit structure, the method comprising:

forming a patterned passivation layer over a metal pad, with a top surface of the metal pad revealed through a first opening in the patterned passivation layer;

applying a polymer layer over the patterned passivation layer, wherein the polymer layer is free from N-Methyl-2-pyrrolidone (NMP), and wherein the polymer layer comprises aliphatic amide as a solvent;

performing a light-exposure process on the polymer layer;

performing a development process on the polymer layer to form a second opening in the polymer layer, wherein the top surface of the metal pad is revealed to the second opening;

baking the polymer layer; and

forming a conductive region comprising a via portion extending into the second opening.

2. The method of claim 1 , wherein the polymer layer comprises alkoxy decane.

3. The method of claim 1 , wherein the baking process is performed at a temperature in a range between about 120° C. and about 210° C.

4. The method of claim 1 , wherein the via portion comprises:

a straight sidewall;

a straight bottom surface; and

a round corner comprising a top end connecting to the straight sidewall, and a bottom end connecting to the straight bottom surface, wherein the round corner has an R-angle smaller than about 4 μm, wherein the R-angle is a diameter of a respective circle to which the round corner fits.

5. The method of claim 4 , wherein the straight sidewall has a tilt angle in a range between about 45 degrees and about 90 degrees.

6. The method of claim 4 , wherein the straight sidewall has a tilt angle in a range between about 70 degrees and about 80 degrees.

7. The method of claim 1 , wherein after the baking process, the polymer layer has a thickness greater than about 5 μm.

8. A method of forming an integrated circuit structure, the method comprising:

applying a polymer layer over a metal pad;

patterning the polymer layer to form an opening in the polymer layer, wherein a top surface of the metal pad is revealed to the opening, and the polymer layer comprises:

a straight sidewall facing the opening; and

a round corner surface comprising a top end connecting to the straight sidewall, and a bottom end joining to the top surface of the metal pad, wherein the round corner surface has an R-angle smaller than about 4 μm, and wherein the R-angle is a diameter of a respective circle to which the round corner surface fits; and

forming a conductive region comprising:

a via portion extending into the opening; and

a bump portion over the polymer layer.

9. The method of claim 8 , wherein the polymer layer, when applied, comprises aliphatic amide as a solvent.

10. The method of claim 8 , wherein the polymer layer, when applied, is free from N-Methyl-2-pyrrolidone (NMP).

11. The method of claim 8 , wherein the polymer layer comprises silicon alkoxide.

12. The method of claim 8 further comprising baking the polymer layer after the polymer layer is patterned, and the baking is performed at a temperature in a range between about 120° C. and about 210° C.

13. A method of forming an integrated circuit structure, the method comprising:

applying a polymer layer over and contacting a metal pad, wherein the polymer layer comprises aliphatic amide as a solvent, and alkoxy decane dissolved in the solvent;

patterning the polymer layer to form an opening in the polymer layer, wherein a top surface of the metal pad is revealed to the opening;

baking the polymer layer; and

forming a conductive region comprising a via portion extending into the opening.

14. The method of claim 13 , wherein the polymer layer is free from N-Methyl-2-pyrrolidone (NMP).

15. The method of claim 14 , wherein the polymer layer is free from NMP at a time the polymer layer is applied.

16. The method of claim 13 , wherein the via portion comprises:

a straight sidewall;

a straight bottom surface; and

a round corner comprising a top end connecting to the straight sidewall, and a bottom end connecting to the straight bottom surface, wherein the round corner has an R-angle smaller than about 4 μm, wherein the R-angle is a diameter of a respective circle to which the round corner fits.

17. The method of claim 16 , wherein the straight sidewall has a tilt angle in a range between about 45 degrees and about 90 degrees.

18. The method of claim 13 , wherein after the polymer layer is baked, the polymer layer has a thickness greater than about 5 μm.

Assignments (2)
CORRECTIVE ASSIGNMENT TO CORRECT THE TYPOGRAPHICAL ERROR IN THE 4TH AND 5TH INVENTORS NAME PREVIOUSLY RECORDED ON REEL 049642 FRAME 0771. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT OF ASSIGNOR'S INTEREST. Recorded Feb 24, 2021
From: CHENG, MING-DA; CHAO, YUNG-CHING; TZENG, CHUN KAI; LIN, CHENG JEN; KANG, CHIN WEI; CHEN, YU-FENG; LII, MIRNG-JI
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 055403/0080 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 1, 2019
From: CHENG, MING-DA; CHAO, YUNG-CHING; TZENG, CHUN KAI; JEN, LIN CHENG; WEI, KANG CHIN; CHEN, YU-FENG; LII, MIRNG-JI
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 049642/0771 →
Continuity (2)
Provisional Application 62738511 · Sep 28, 2018
Related Publication 20200105696A1 · Apr 2, 2020