IP Library Granted Patent US 10,672,689
Granted Patent B2
US 10,672,689 · App. 16/460,704 · Granted Jun 2, 2020

Protection from ESD during the manufacturing process of semiconductor chips

Inventors: Frederick Ray Gomez (Calamba, PH); Tito Mangaoang, Jr. (Pasig, PH); Jefferson Talledo (Calamba, PH)
Assignee: STMICROELECTRONICS, INC.
H01L23/4952H01L21/4832H01L21/56H01L21/561H01L23/49548H01L23/60H01L22/12H01L23/3107H01L24/29H01L24/32H01L24/48H01L24/49H01L24/73H01L24/83H01L24/85H01L24/92H01L2223/544H01L2224/04042H01L2224/2919H01L2224/32245H01L2224/48091H01L2224/48247H01L2224/49052H01L2224/73265H01L2224/83855H01L2224/85013H01L2224/85424H01L2224/85447H01L2224/92247H01L2224/97
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Quick Facts
Patent No.
US 10,672,689
App. No.
16/460,704
Granted
Jun 2, 2020
Kind
B2
Abstract

According to principles of the disclosure as explained herein, selected leads are electrically connected through metal strips to the lead frame until the end of the manufacturing process. The lead frame is grounded through the manufacturing process to prevent any ESD event from causing damage to the protected leads. In the final singulation step, the leads are electrically isolated from each other and from the lead frame, thus maintaining protection from a potential ESD event up until the final package singulation step.

Claims (52)

1. A method comprising:

forming a plating layer on a first portion of a lead frame, the forming the plating layer including connecting at least one lead of a plurality of leads of the lead frame to a bus line of the lead frame;

removing a second portion of the lead frame, the removing including maintaining the plating layer connecting the least one lead of the lead frame to the bus line;

grounding the lead frame, the grounding including grounding the at least one lead;

subjecting the lead frame to an electrostatic discharge event; and

separating the lead frame into a plurality of packages, the separating including removing the bus line of the lead frame to electrically isolate the at least one lead.

2. The method of claim 1 further comprising, before forming the plating layer:

attaching a semiconductor die to a first side of the lead frame, wherein forming the plating layer on the first portion of the lead frame includes forming the plating layer on a second side of the lead frame opposite the first side of the lead frame.

3. The method of claim 2 further comprising, after attaching the semiconductor die:

connecting an electrically conductive wire between the semiconductor die and a lead of the plurality of leads of the lead frame; and

encapsulating the semiconductor die, the electrically conductive wire, and the plurality of leads with a molding compound.

4. The method of claim 1 wherein separating the lead frame includes sawing the lead frame with a mechanical saw.

5. The method of claim 1 , further comprising:

attaching a semiconductor die to the lead frame; and

testing the lead frame, the testing including:

subjecting the lead frame to a plurality of electrostatic discharge events during a testing sequence; and

inspecting the plurality of leads of the lead frame after each electrostatic discharge event, the inspecting including identifying at least one damaged lead damaged by at least one electrostatic discharge event of the plurality of electrostatic discharge events of the testing sequence.

6. The method of claim 5 wherein attaching the semiconductor die to the lead frame includes attaching a dummy semiconductor die to the lead frame.

7. The method of claim 5 wherein attaching the semiconductor die to the lead frame includes attaching a fully operational die to the lead frame.

8. The method of claim 1 wherein subjecting the lead frame to the electrostatic discharge event includes passing the lead frame through a waterjet washing station.

9. A method comprising:

attaching a semiconductor die to a first side of a first lead frame;

testing the first lead frame, the testing including:

subjecting the first lead frame to at least one electrostatic discharge event during a testing sequence; and

inspecting a plurality of leads of the first lead frame after each electrostatic discharge event, the inspecting including identifying at least one damaged lead damaged by each electrostatic discharge event of the at least one electrostatic discharge event of the testing sequence;

forming a plating layer on a second lead frame, the forming the plating layer including connecting at least one lead of a plurality of leads of the second lead frame at a location on the second lead frame corresponding to a location of the at least one damaged lead of the first lead frame to a bus line of the second lead frame;

grounding the second lead frame, the grounding including grounding the at least one lead of the second lead frame;

cleaning the second lead frame; and

separating the second lead frame into a plurality of packages, the separating including electrically isolated the at least one lead of the second lead frame.

10. The method of claim 9 wherein attaching the semiconductor die to the first side of the lead frame includes attaching a dummy semiconductor die to the first side of the first lead frame.

11. The method of claim 9 wherein attaching the semiconductor die to the first side of the lead frame includes attaching a fully operational semiconductor die to the first side of the first lead frame.

12. The method of claim 9 wherein inspecting the plurality of leads includes visually inspecting the plurality of leads.

13. The method of claim 9 wherein inspecting the plurality of leads includes inspecting the plurality of leads with a machine.

14. The method of claim 9 wherein inspecting the plurality of leads includes electrically testing the first lead frame and the semiconductor die to determine the at least one damaged lead through parametric responses.

15. A method, comprising:

attaching a semiconductor die to a first side of a first lead frame including a plurality of leads;

connecting at least one lead line between a first one of the plurality of leads on a second side of the first lead frame and a bus line of the first lead frame;

grounding the first lead frame, the grounding including ground the first one of the plurality of leads;

subjecting the first lead frame to a first electrostatic discharge event; and

separating the first lead frame into a plurality of first packages, the separating including removing the bus line of the lead frame to electrically isolate the first one of the plurality of leads.

16. The method of claim 15 wherein connecting at least one lead line includes connecting a first lead line and a second lead line to the first one of the plurality of leads.

17. The method of claim 15 further comprising, after attaching the semiconductor die:

forming a plating layer on a portion of the second side of the lead frame, forming the plating layer including connecting a second one of the plurality of leads to the bus line of the lead frame.

18. The method of claim 15 , further comprising, after separating the first lead frame:

testing the lead frame, the testing including inspecting the plurality of leads of the lead frame, the inspecting including identifying at least one damaged lead damaged by the first electrostatic discharge event.

19. The method of claim 18 further comprising:

attaching a semiconductor die to a first side of a second lead frame including a plurality of leads;

connecting at least one lead line between a lead of the plurality of leads in a location on a second side of the second lead frame corresponding to a location of the at least one damaged lead of the plurality of leads of the first lead frame to a bus line of the second lead frame;

grounding the second lead frame, the grounding including ground the lead;

subjecting the second lead frame to a second electrostatic discharge event; and

separating the second lead frame into a plurality of second packages, the separating including removing the bus line of the second lead frame to electrically isolate the lead of the plurality of leads of the second lead frame.

20. The method of claim 19 wherein connecting at least one lead line between the lead of the plurality of leads includes connecting a first lead line and a second lead line to the lead of the plurality of leads.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2024
From: STMICROELECTRONICS, INC.
To: STMICROELECTRONICS INTERNATIONAL N.V.
Reel/Frame 068025/0112 →
Continuity (2)
Division 15636533 · Jun 28, 2017
Related Publication 20190326201A1 · Oct 24, 2019