IP Library › Granted Patent US 11,316,000
Granted Patent B2
US 11,316,000 · App. 16/466,531 · Granted Apr 26, 2022

Array substrate including metal strip, manufacturing method thereof and display device

Inventors: Hongwei Ma (Beijing, CN); Kai Zhang (Beijing, CN); Yunsheng Xiao (Beijing, CN); Xiangdan Dong (Beijing, CN)
Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.; BOE TECHNOLOGY GROUP CO., LTD.
H01L27/3276H01L27/124H01L27/1218H01L27/1262H01L27/1259H01L27/3258H01L27/3262
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Quick Facts
Patent No.
US 11,316,000
App. No.
16/466,531
Granted
Apr 26, 2022
Kind
B2
Abstract

An array substrate, a manufacturing method thereof and a display device are disclosed. The array substrate includes a base substrate; a first metal layer on the base substrate; a first insulating layer on the first metal layer; a second metal layer on the first insulating layer; and a second insulating layer located on the second metal layer. The array substrate includes a display region and a peripheral region surrounding the display region, the first metal layer includes a plurality of signal lines in the peripheral region, the second insulating layer includes at least one groove overlapping at least two signal lines, the second metal layer includes a metal strip in the peripheral region, and in the area where the groove overlaps the signal lines, an orthographical projection on the base substrate fall into the orthographic projection of the metal strip on the base substrate.

Claims (37)

1. An array substrate comprising:

a base substrate;

a first metal layer on the base substrate;

a first insulating layer on one side of the first metal layer away from the base substrate;

a second metal layer on one side of the first insulating layer away from the base substrate; and

a second insulating layer on one side of the second metal layer away from the base substrate,

wherein the array substrate comprises a display area and a peripheral area surrounding the display area, the first metal layer comprises a plurality of signal lines in the peripheral area, the second insulating layer comprises at least one groove overlapping at least two signal lines in the plurality of signal lines in the peripheral area, the second metal layer comprises at least one metal strip in the peripheral area, and

in an area where the groove overlaps the signal lines, an orthographic projection of the signal lines on the base substrate falls into an orthographic projection of the metal strip on the base substrate.

2. The array substrate according to claim 1 , wherein the at least one metal strip comprises a plurality of metal strips, the plurality of metal strips are arranged one-to-one corresponding to the plurality of signal lines, and an orthographic projection of each signal line on the base substrate falls into an orthographic projection of a corresponding metal strip arranged on the base substrate in an area where the groove overlaps with the signal lines.

3. The array substrate according to claim 2 , wherein the plurality of signal lines extend into the display region.

4. The array substrate according to claim 2 , wherein the second metal layer comprises a conductive pattern in the display region, and each of the metal strips is insulated from the conductive pattern.

5. The array substrate according to claim 2 , wherein a material of the first insulating layer comprises an inorganic insulating material and a material of the second insulating layer comprises an inorganic insulating material.

6. The array substrate according to claim 2 , wherein the groove penetrates the first insulating layer in a direction perpendicular to the base substrate in an area where the metal strip is not provided in the peripheral region.

7. The array substrate according to claim 2 , wherein the first metal layer is a first gate electrode metal layer and the second metal layer is a second gate electrode metal layer.

8. The array substrate according to claim 1 , wherein a width of each of the metal strips is larger than a width of each of the signal lines in the area where the groove overlaps the signal lines.

9. The array substrate according to claim 1 , wherein a material of the first insulating layer comprises an inorganic insulating material and a material of the second insulating layer comprises an inorganic insulating material.

10. The array substrate according to claim 1 , wherein the groove penetrates the first insulating layer in a direction perpendicular to the base substrate in an area where the metal strip is not provided in the peripheral region.

11. The array substrate according to claim 1 , wherein the first metal layer is a first gate electrode metal layer and the second metal layer is a second gate electrode metal layer.

12. The array substrate according to claim 1 , wherein the second insulating layer comprises an interlayer dielectric layer.

13. The array substrate according to claim 1 , further comprising:

a third metal layer on one side of the second insulating layer away from the second metal layer,

wherein the third metal layer comprises a metal residue located at the bottom corner of the groove in the peripheral region.

14. The array substrate of claim 13 , wherein the third metal layer comprises at least one of a source electrode, a drain electrode, and a source-drain signal line in the display region.

15. The array substrate according to claim 14 , further comprising:

a passivation layer disposed on one side of the third metal layer away from the second insulating layer; and

a pixel electrode in the display region and on one side of the passivation layer away from the third metal layer.

16. A display device comprising the array substrate according to claim 1 .

17. A method of manufacturing an array substrate, comprising:

forming a first metal layer on the base substrate;

forming a first insulating layer on one side of the first metal layer away from the base substrate;

forming a second metal layer on a side of the first insulating layer away from the base substrate;

forming a second insulating layer on one side of the second metal layer away from the base substrate; and

etching the second insulating layer to form at least one groove,

wherein the array substrate comprises a display area and a peripheral area surrounding the display area, the first metal layer comprises a plurality of signal lines in the peripheral area, the groove overlaps at least two signal lines in the plurality of signal lines, the second metal layer comprises at least one metal strip in the peripheral area, and in an area where the groove overlaps the signal lines, an orthographic projection of the signal lines on the base substrate falls into an orthographic projection of the metal strips on the base substrate.

18. The method of manufacturing the array substrate according to claim 17 , wherein the at least one metal strip comprises a plurality of metal strips, the plurality of metal strips are arranged one-to-one corresponding to the plurality of signal lines, and an orthographic projection of each of the signal lines on the base substrate falls into an orthographic projection of a corresponding metal strip arranged on the base substrate in the area where the groove overlaps with the signal lines.

19. The method of manufacturing the array substrate according to claim 14 , wherein a width of each of the metal strips is larger than a width of each of the signal lines in the area where the groove overlaps the signal lines.

20. The method of manufacturing the array substrate according to claim 14 , wherein the second metal layer comprises a conductive pattern in the display region, each of the metal strips is insulated from the conductive pattern, and the metal strips and the conductive pattern are manufactured in a same mask process.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 4, 2019
From: MA, HONGWEI
To: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.; BOE TECHNOLOGY GROUP CO., LTD.
Reel/Frame 049365/0402 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 4, 2019
From: ZHANG, KAI
To: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.; BOE TECHNOLOGY GROUP CO., LTD.
Reel/Frame 049365/0734 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 4, 2019
From: XIAO, YUNSHENG
To: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.; BOE TECHNOLOGY GROUP CO., LTD.
Reel/Frame 049365/0834 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 4, 2019
From: DONG, XIANGDAN
To: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.; BOE TECHNOLOGY GROUP CO., LTD.
Reel/Frame 049365/0887 →
Priority Claims (1)
CN 201810208808.7 · Mar 14, 2018 · national
Continuity (1)
Related Publication 20210358956A1 · Nov 18, 2021