Structure for radio frequency applications

1. A structure for RF applications, comprising:

a high-resistivity support substrate having a front surface defining a main plane of a coordinate system;

a charge-trapping layer arranged on the front surface of the support substrate;

a first dielectric layer arranged on the charge-trapping layer;

an active layer arranged on the first dielectric layer such that the first dielectric layer is between the active layer and the charge-trapping layer; and

at least one buried electrode arranged above or inside the charge-trapping layer, the buried electrode comprising a conductive layer and a second dielectric layer.

2. The structure of claim 1 , wherein the second dielectric layer has a thickness in a range extending from 5 nm to 100 nm.

3. The structure of claim 1 , wherein the conductive layer comprises a material selected from among monocrystalline silicon, polycrystalline silicon, and amorphous silicon.

4. The structure of claim 1 , wherein the conductive layer has a thickness in a range extending from 50 nm to 500 nm.

5. The structure of claim 1 , wherein the conductive layer has a resistivity of several ohms.cm to several thousand ohms.cm.

6. The structure of claim 1 , wherein the electrode is arranged between the active layer and the first dielectric layer, the second dielectric layer being in contact with the active layer along the main plane.

7. The structure of claim 1 , wherein the electrode is arranged between the first dielectric layer and the charge-trapping layer, the second dielectric layer being in contact with the charge-trapping layer, along the main plane.

8. A structure for RF applications, comprising:

a high-resistivity support substrate having a front surface defining a main plane of a coordinate system,

a charge-trapping layer arranged on the front surface of the support substrate;

a first dielectric layer arranged on the charge-trapping layer;

an active layer arranged on the first dielectric layer; and

at least one buried electrode arranged inside the charge-trapping layer, the buried electrode comprising a conductive layer and a second dielectric layer, wherein the second dielectric layer is in contact with the front surface of the support substrate along the main plane, and wherein the electrode comprises a plurality of insulating walls extending between the first and second dielectric layers and defining a plurality of conductive blocks of the conductive layer, each conductive block being insulated from at least one trapping area forming the charge-trapping layer by the insulating walls.

9. A structure for RF applications, comprising:

a high-resistivity support substrate having a front surface defining a main plane of a coordinate system;

a charge-trapping layer arranged on the front surface of the support substrate;

a first dielectric layer arranged on the charge-trapping layer;

an active layer arranged on the first dielectric layer; and

at least one buried electrode arranged above or inside the charge-trapping layer, the buried electrode comprising a conductive layer and a second dielectric layer, wherein the conductive layer has two surfaces parallel to the main plane, one surface of the two surfaces in contact with the first dielectric layer and another surface of the two surfaces in contact with the second dielectric layer.

10. The structure of claim 9 , wherein the electrode comprises a plurality of insulating walls extending between the first and second dielectric layers and segmenting the conductive layer into a plurality of conductive blocks, the blocks being insulated from one another by the insulating walls.

11. The structure of claim 10 , wherein the electrode is arranged between the active layer and the first dielectric layer, the second dielectric layer being in contact with the active layer parallel to the main plane.

12. The structure of claim 10 , wherein the electrode is arranged between the first dielectric layer and the charge-trapping layer, the second dielectric layer being in contact with the charge-trapping layer, parallel to the main plane.

13. The structure of claim 12 , wherein the electrode is discontinuous in the main plane and a plurality of charge-trapping areas extend between the first dielectric layer and the charge-trapping layer, the charge-trapping areas being insulated from the conductive blocks by the insulating walls.

14. The structure of claim 9 , wherein the electrode is arranged in the charge-trapping layer, the second dielectric layer being in contact with the front surface of the support substrate along the main plane, and wherein the electrode comprises a plurality of insulating walls extending between the first and second dielectric layers and defining a plurality of conductive blocks of the conductive layer, each conductive block being insulated from at least one trapping area forming the charge-trapping layer by the insulating walls.

15. The structure of claim 14 , wherein at least one conductive block is electrically connected to a contact pad arranged on a free surface of the active layer by a conductive via passing through a portion of the structure from the conductive block to the contact pad.

16. The structure of claim 15 , further comprising a device in and/or on the active layer, the device comprising at least one transistor including a gate electrode arranged on the free surface of the active layer, the gate electrode located opposite at least one conductive block of the buried electrode.

17. The structure of claim 10 , wherein at least one conductive block is electrically connected to a contact pad arranged on a free surface of the active layer by a conductive via passing through a portion of the structure from the conductive block to the contact pad.

18. The structure of claim 17 , further comprising a device in and/or on the active layer, the device comprising at least one transistor including a gate electrode arranged on the free surface of the active layer, the gate electrode located opposite at least one conductive block of the buried electrode.