Granted Patent B2

US 12,418,120 · App. 17/816,599 · Granted Sep 16, 2025

Inventors: Eric Desbonnets (Lumbin, FR); Bernard Aspar (Saint-Ismier, FR)

Assignee: Soitec

H01Q23/00H01L21/76251H01Q1/2283H10D30/0323H10D30/6711H10D30/6758

Abstract

Claims (32)

1. A structure for RF applications, comprising:

a support substrate;

a charge-trapping layer arranged on the support substrate;

a first dielectric layer arranged on the charge-trapping layer such that the charge-trapping layer is disposed between the first dielectric layer and the support substrate;

an active layer arranged on the first dielectric layer, the active layer comprising a piezoelectric material; and

at least one buried electrode arranged between the active layer and the support substrate, the buried electrode comprising a conductive layer and a second dielectric layer;

wherein the conductive layer has two parallel main surfaces, one main surface of the two parallel main surfaces in contact with the first dielectric layer and another main surface of the two parallel main surfaces in contact with the second dielectric layer.

2. The structure of claim 1 , wherein the at least one buried electrode comprises a plurality of insulating walls extending between the first dielectric layer and the second dielectric layer and segmenting the conductive layer into a plurality of conductive blocks, the conductive blocks being insulated from one another by the insulating walls.

3. The structure of claim 1 , wherein the at least one buried electrode is arranged between the active layer and the first dielectric layer, and the second dielectric layer is in contact with the active layer.

4. The structure of claim 1 , wherein the at least one buried electrode is arranged between the first dielectric layer and the charge-trapping layer, the second dielectric layer being in contact with the charge-trapping layer.

5. The structure of claim 4 , wherein the at least one buried electrode is discontinuous and a plurality of charge-trapping areas extend between the first dielectric layer and the charge-trapping layer and segment the conductive layer into a plurality of conductive blocks, the charge-trapping areas being insulated from the conductive blocks by insulating walls.

6. The structure of claim 1 , wherein the at least one buried electrode is arranged in the charge-trapping layer, the second dielectric layer being in contact with a front surface of the support substrate, and wherein the at least one buried electrode comprises a plurality of insulating walls extending between the first and second dielectric layers and defining a plurality of conductive blocks, each conductive block being insulated from at least one charge-trapping area of the charge-trapping layer by the insulating walls.

7. The structure of claim 6 , wherein at least one conductive block is electrically connected to a contact pad arranged on a free surface of the active layer by a conductive via passing through a portion of the structure from the at least one conductive block to the contact pad.

8. The structure of claim 1 , wherein the second dielectric layer has a thickness in a range extending from 5 nm to 100 nm.

9. The structure of claim 1 , wherein the conductive layer comprises a material selected from among monocrystalline silicon, polycrystalline silicon, and amorphous silicon.

10. The structure of claim 1 , wherein the conductive layer has a thickness in a range extending from 50 nm to 500 nm.

11. The structure of claim 1 , wherein the conductive layer has a resistivity of several ohms·cm to several thousand ohms·cm.

12. The structure of claim 1 , wherein the piezoelectric material comprises a material selected from among lithium niobate, lithium tantalate, quartz, aluminum nitride.

13. The structure of claim 1 , wherein the first dielectric layer comprises a material selected from among silicon dioxide, silicon nitride, aluminum oxide.

14. A structure for RF applications, comprising:

a high-resistivity support substrate having a front surface defining a main plane of a coordinate system;

a charge-trapping layer arranged on the front surface of the support substrate;

a first dielectric layer arranged on the charge-trapping layer;

an active layer arranged on the first dielectric layer, the active layer comprising a piezoelectric material; and

at least one buried electrode arranged inside the charge-trapping layer.

15. The structure of claim 14 , wherein the at least one buried electrode comprises a conductive layer and a second dielectric layer, wherein the second dielectric layer is in contact with the front surface of the support substrate along the main plane, and wherein the at least one buried electrode comprises a plurality of insulating walls extending between the first dielectric layer and the second dielectric layer and defining a plurality of conductive blocks of the conductive layer, each conductive block being insulated from at least one charge-trapping area of the charge-trapping layer by the insulating walls.

16. The structure of claim 15 , wherein at least one conductive block is electrically connected to a contact pad arranged on a free surface of the active layer by a conductive via passing through a portion of the structure from the conductive block to the contact pad.

17. The structure of claim 16 , further comprising a device in and/or on the active layer.

18. The structure of claim 15 , wherein the second dielectric layer has a thickness in a range extending from 5 nm to 100 nm.

19. The structure of claim 15 , wherein the conductive layer comprises a material selected from among monocrystalline silicon, polycrystalline silicon, and amorphous silicon.

20. The structure of claim 15 , wherein the conductive layer has a thickness in a range extending from 50 nm to 500 nm.

21. The structure of claim 15 , wherein the conductive layer has a resistivity of several ohms·cm to several thousand ohms·cm.

Priority Claims (1)

Continuity (3)

References Cited (55)