IP Library Granted Patent US 11,069,737
Granted Patent B2
US 11,069,737 · App. 16/505,283 · Granted Jul 20, 2021

Shallow trench textured regions and associated methods

Inventors: Homayoon Haddad (Beaverton, OR); Jutao Jiang (Tigard, OR)
Assignee: SiOnyx, LLC
H01L27/14643B23K26/355B82Y40/00H01L27/1463H01L27/1464H01L27/14625H01L27/14629H01L27/14632H01L27/14689H01L31/028H01L31/02327H01L31/182
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,069,737
App. No.
16/505,283
Granted
Jul 20, 2021
Kind
B2
Abstract

Photosensitive devices and associated methods are provided. In one aspect, for example, a photosensitive imager device can include a semiconductor layer having multiple doped regions forming a least one junction, a textured region coupled to the semiconductor layer and positioned to interact with electromagnetic radiation. The textured region can be formed from a series of shallow trench isolation features.

Claims (72)

1. A photosensitive imager device capable of detecting visible and infrared electromagnetic radiation, comprising:

a semiconductor layer having a light incident side and an opposed side, said semiconductor layer having multiple doped regions forming at least one junction,

a textured region comprising a plurality of surface features configured to interact with incident electromagnetic radiation so as to increase the quantum efficiency of the device, wherein the surface features are arranged according to a pattern,

a support substrate coupled to said semiconductor layer, and

a first bonding layer disposed between the semiconductor layer and the support substrate.

2. The device of claim 1 , wherein the textured region is located on the light incident side of the semiconductor layer.

3. The device of claim 2 , further comprising a device layer coupled to the semiconductor layer on said side opposed to the light incident side.

4. The device of claim 2 , wherein the textured region is formed by etching.

5. The device of claim 4 , wherein said surface features comprise pyramids.

6. The device of claim 2 , further comprising a reflector layer disposed between the textured layer and the support substrate.

7. The device of claim 1 , further comprising deep trench isolation for isolating the device.

8. The device of claim 7 , wherein said deep trench isolation provides light trapping functionality.

9. The device of claim 1 , wherein the semiconductor layer is single crystal silicon.

10. The device of claim 1 , wherein the semiconductor layer comprises silicon and germanium.

11. The device of claim 1 , wherein the surface features are formed in the semiconductor layer.

12. The device of claim 1 , wherein the surface features have a substantially uniform height.

13. The device of claim 1 , wherein the surface features are not uniform in height.

14. The device of claim 1 , wherein said first bonding layer comprises any of silicon oxide, silicon nitride and amorphous silicon.

15. The device of claim 1 , wherein said semiconductor layer has a thickness in a range of about 1 micron to about 10 microns.

16. The device of claim 15 , wherein the device exhibits a quantum efficiency of at least about 35% for electromagnetic radiation at a wavelength of about 940 nm.

17. The device of claim 1 , wherein said bonding layer has a thickness in a range of about 30 nm to about 3 microns.

18. The device of claim 1 , wherein said plurality of surface features have a height in a range of about 50 nm to about 2 microns.

19. The device of claim 1 , wherein said plurality of surface features have a height in a range from about 0.35 microns to about 0.7 microns.

20. The device of claim 1 , wherein said plurality of surface features are formed by using a patterned mask and photolithography followed by etching.

21. The device of claim 1 , wherein said plurality of surface features comprise multiple etched levels.

22. The device of claim 1 , wherein said textured region increases optical absorption of the semiconductor layer over an electromagnetic spectrum range of at least about 700 nm to about 1100 nm.

23. The device of claim 1 , further comprising a second bonding layer positioned between the first bonding layer and the support substrate.

24. The device of claim 1 , wherein the pattern is an at least substantially uniform grid.

25. The device of claim 1 , wherein the pattern is a non-uniform arrangement.

26. A method of making a photosensitive image device, comprising:

providing a semiconductor layer having a light incident side and an opposed side, said semiconductor layer having multiple doped regions forming at least one junction;

providing a support substrate;

bonding the semiconductor layer to the support substrate;

creating a plurality of surface features on one of the semiconductor layer and the support substrate, wherein the surface features are formed via etching;

depositing an oxide material within at least a portion of the semiconductor layer or support substrate removed during etching; and

processing the region of the semiconductor layer or support substrate comprising the surface features with CMP after depositing the oxide material.

27. The method of claim 26 , wherein bonding the semiconductor layer to the support substrate comprises:

depositing a first bonding layer onto the semiconductor layer; and

bonding the first bonding layer to a second bonding layer disposed on the support substrate.

28. The method of claim 26 , wherein the plurality of surface features are formed on the light incident side of the semiconductor layer.

29. The method of claim 26 , wherein depositing the oxide material comprises at least partially filling one of trenches, holes, pits, and cones formed in the semiconductor layer during etching.

30. The method of claim 26 , wherein the surface features are formed by shallow trench isolation etching.

31. The method of claim 26 , wherein the surface features are formed in the semiconductor layer.

32. A photosensitive imager device capable of detecting visible and infrared electromagnetic radiation, comprising:

a semiconductor layer having a light incident side and an opposed side, said semiconductor layer having multiple doped regions forming at least one junction,

a textured region comprising a plurality of surface features configured to interact with incident electromagnetic radiation so as to increase the quantum efficiency of the device,

a support substrate coupled to said semiconductor layer, and

a first bonding layer disposed between the semiconductor layer and the support substrate,

wherein the device exhibits a quantum efficiency of at least about 35% for electromagnetic radiation at a wavelength of about 940.

33. The device of claim 32 , wherein the textured region is located on the light incident side of the semiconductor layer.

34. The device of claim 33 , further comprising a device layer coupled to the semiconductor layer on said side opposed to the light incident side.

35. The device of claim 33 , wherein the textured region is formed by etching.

36. The device of claim 35 , wherein said surface features comprise pyramids.

37. The device of claim 33 , further comprising a reflector layer disposed between the textured layer and the support substrate.

38. The device of claim 32 , further comprising deep trench isolation for isolating the device.

39. The device of claim 38 , wherein said deep trench isolation provides light trapping functionality.

40. The device of claim 32 , wherein the semiconductor layer is single crystal silicon.

41. The device of claim 32 , wherein the semiconductor layer comprises silicon and germanium.

42. The device of claim 32 , wherein the surface features are formed in the semiconductor layer.

43. The device of claim 32 , wherein the surface features have a substantially uniform height.

44. The device of claim 32 , wherein the surface features are not uniform in height.

45. The device of claim 32 , wherein said first bonding layer comprises any of silicon oxide, silicon nitride and amorphous silicon.

46. The device of claim 32 , wherein said semiconductor layer has a thickness in a range of about 1 micron to about 10 microns.

47. The device of claim 32 , wherein said bonding layer has a thickness in a range of about 30 nm to about 3 microns.

48. The device of claim 32 , wherein said plurality of surface features have a height in a range of about 50 nm to about 2 microns.

49. The device of claim 32 , wherein said plurality of surface features have a height in a range from about 0.35 microns to about 0.7 microns.

50. The device of claim 32 , wherein said plurality of surface features are formed by using a patterned mask and photolithography followed by etching.

51. The device of claim 32 , wherein said plurality of surface features comprise multiple etched levels.

52. The device of claim 32 , wherein said textured region increases optical absorption of the semiconductor layer over an electromagnetic spectrum range of at least about 700 nm to about 1100 nm.

53. The device of claim 32 , further comprising a second bonding layer positioned between the first bonding layer and the support substrate.

54. The device of claim 32 , wherein the surface features are arranged according to a pattern that is an at least substantially uniform grid.

55. The device of claim 32 , wherein the surface features are arranged according to a pattern that is a non-uniform arrangement.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 18, 2020
From: HADDAD, HOMAYOON; JIANG, JUTAO
To: SIONYX, INC.
Reel/Frame 053523/0520 →
CONVERSION Recorded Aug 18, 2020
From: SIONYX, INC.
To: SIONYX, LLC
Reel/Frame 053526/0001 →
Continuity (5)
Continuation 15614256 · Jun 5, 2017
Continuation 14884181 · Oct 15, 2015
Continuation 14084392 · Nov 19, 2013
Provisional Application 61841326 · Jun 29, 2013
Related Publication 20190333959A1 · Oct 31, 2019