Through silicon via optimization for three-dimensional integrated circuits

1. A method for forming a semiconductor structure, comprising:

providing a first substrate in a first chip;

depositing a first conductive line in the first substrate;

depositing a first conductive island in the first substrate and on a top surface of the first conductive line;

depositing a first plurality of vias in the first conductive island and on the top surface of the first conductive line;

planarizing top surfaces of the first conductive island and the first plurality of vias;

forming a second conductive line in a second chip and in contact with a second conductive island;

bonding the second chip to the first chip, comprising bonding the second conductive island of the second chip to the first conductive island of the first chip; and

electrically coupling the first and second conductive lines through the first and second conductive islands.

2. The method of claim 1 , wherein bonding the second chip to the first chip comprises bonding a second plurality of vias of the second chip to the first plurality of vias of the first chip.

3. The method of claim 1 , wherein depositing the first conductive island comprises depositing copper, cobalt, aluminum, tungsten, or doped polysilicon.

4. The method of claim 1 , wherein bonding the second chip to the first chip comprises hybrid bonding the second chip to the first chip.

5. The method of claim 1 , wherein bottom surfaces of the first plurality of vias are in contact with the top surface of the first conductive line.

6. A method, comprising:

forming a first chip, comprising:

depositing a first conductive line;

forming a first conductive island on the first conductive line;

forming a first plurality of vias in the first conductive island; and

electrically coupling the first plurality of vias to the first conductive line;

forming a second chip, comprising:

depositing a second conductive line;

forming a second conductive island on the second conductive line;

forming a second plurality of vias in the second conductive island; and

electrically coupling the second plurality of vias to the second conductive line;

bonding the first chip to the second chip; and

electrically coupling the first and second conductive lines through the first and second conductive islands.

7. The method of claim 6 , wherein bonding the first to the second chip comprises:

bonding top surfaces of the first and second conductive islands; and

bonding top surfaces of the first and second pluralities of vias.

8. The method of claim 6 , wherein forming the first plurality of vias comprises:

forming a plurality of openings in the first conductive island; and

depositing a conductive material in the plurality of openings.

9. The method of claim 6 , further comprising electrically coupling the first and second conductive lines to power grid lines.

10. The method of claim 6 , wherein:

forming the first conductive island comprises depositing a first conductive material; and

forming the first plurality of vias comprises depositing a second conductive material different from the first conductive material.

11. The method of claim 10 , wherein the first conductive material comprises a first resistivity and the second conductive material comprises a second resistivity greater than the first resistivity.

12. The method of claim 6 , wherein depositing the second conductive material comprises depositing copper, cobalt, aluminum, tungsten, or doped polysilicon.

13. A method, comprising:

forming a first chip, comprising:

forming a first power grid (PG) line in a first substrate;

forming a first conductive island in the first substrate and on a top surface of the first PG line;

etching the first conductive island to form a first plurality of openings, wherein the first plurality of openings expose portions of the top surface of the first PG line; and

depositing a first conductive material in the first plurality of openings and on the exposed portions of the top surface of the first PG line to form a first plurality of vias, wherein the first plurality of vias is electrically coupled to the first PG line;

forming a second chip, comprising:

forming a second PG line in a second substrate;

forming a second conductive island in the second substrate and on the second PG line;

etching the second conductive island to form a second plurality of openings; and

depositing a second conductive material in the second plurality of openings to form a second plurality of vias, wherein the second plurality of vias is electrically coupled to the second PG line; and

bonding the first and second chips at top surfaces of the first and second conductive islands and at top surfaces of the first and second pluralities of vias, respectively.

14. The method of claim 13 , wherein the first and second pluralities of openings expose portions of the first and second PG lines, respectively.

15. The method of claim 13 , wherein an electrical resistivity of the first conductive material is lower than an electrical resistivity of the first conductive island.

16. The method of claim 13 , further comprising:

performing a first planarization process such that the top surfaces of the first conductive island and the first plurality of vias are substantially level; and

performing a second planarization process such that the top surfaces of the second conductive island and the second plurality of vias are substantially level.

17. The method of claim 13 , wherein bottom surfaces of the first plurality of vias are in contact with the top surface of the first PG line.

18. The method of claim 13 , further comprising electrically coupling the first and second PG lines through the first and second conductive islands.