Methods of forming gate structures for transistor devices on an IC product
One illustrative method disclosed herein includes forming 1st and 2nd sacrificial gate structures for, respectively, 1st and 2nd devices, removing 1st and 2nd sacrificial gate electrodes from the 1st and 2nd sacrificial gate structures so as to at least partially define, respectively, 1st and 2nd replacement gate (RMG) cavities, and removing the 2nd sacrificial gate insulation layer from the 2nd RMG cavity while leaving the 1st sacrificial gate insulation layer in position in the 1st RMG cavity. The method also includes forming a conformal gate insulation layer in both the 1st and 2nd RMG cavities, removing the conformal gate insulation layer and the 1st sacrificial gate insulation layer from the 1st RMG cavity while leaving the conformal gate insulation layer in the 2nd RMG cavity, and performing an oxidation process to form an interfacial gate insulation layer only in the 1st RMG cavity.
1. A method of forming first and second replacement gate structures for, respectively, first and second transistor devices that are formed above a semiconductor substrate, the method comprising:
forming first and second sacrificial gate structures for, respectively, the first and second transistor devices, the first and second sacrificial gate structures comprising, respectively, first and second sacrificial gate insulation layers and, respectively, first and second sacrificial gate electrodes;
removing the first and second sacrificial gate electrodes so as to at least partially define, respectively, first and second replacement gate (RMG) cavities for, respectively, the first and second transistor devices;
removing the second sacrificial gate insulation layer from the second RMG cavity while leaving the first sacrificial gate insulation layer in position in the first RMG cavity;
performing a conformal deposition process to form a conformal gate insulation layer in both the first and second RMG cavities;
performing at least one process operation to remove the conformal gate insulation layer and the first sacrificial gate insulation layer from the first RMG cavity while leaving the conformal gate insulation layer in position in the second RMG cavity; and
performing an oxidation process to form an interfacial gate insulation layer only in the first RMG cavity.
2. The method of claim 1 , wherein the first and second transistor devices are FINFET transistor devices, the semiconductor substrate is a bulk silicon substrate, the first and second sacrificial gate insulation layers comprise silicon dioxide and the first and second sacrificial gate electrodes comprise one of polysilicon or amorphous silicon.
3. The method of claim 1 , wherein, prior to removing the second sacrificial gate insulation layer from the second RMG cavity, the method comprises forming a first patterned etch mask that covers the first transistor device and exposes the second transistor device for further processing.
4. The method of claim 3 , wherein, prior to performing the conformal deposition process to form the conformal gate insulation layer, the method comprises removing the first patterned etch mask.
5. The method of claim 4 , wherein, prior to performing the at least one process operation to remove the conformal gate insulation layer and the first sacrificial gate insulation layer from the first RMG cavity, the method further comprises forming a second patterned etch mask that covers the second transistor device and exposes the first transistor device for further processing.
6. The method of claim 5 , wherein, prior to performing the oxidation process to form the interfacial gate insulation layer only in the first RMG cavity, the method comprises removing the second patterned etch mask.
7. The method of claim 1 , wherein removing the second sacrificial gate insulation layer from the second RMG cavity exposes a surface of the semiconductor substrate within the second RMG cavity.
8. The method of claim 1 , wherein performing the at least one process operation to remove the conformal gate insulation layer and the first sacrificial gate insulation layer from the first RMG cavity exposes a surface of the semiconductor substrate within the first RMG cavity.
9. The method of claim 1 , wherein performing the at least one process operation to remove the conformal gate insulation layer and the first sacrificial gate insulation layer from the first RMG cavity exposes a surface of the semiconductor substrate within the first RMG cavity.
10. The method of claim 9 , wherein performing the oxidation process forms the interfacial gate insulation layer on the exposed surface of the semiconductor substrate within the first RMG cavity.
11. The method of claim 1 , wherein the first transistor device has a first channel length and the second transistor device has a second channel length, wherein the first channel length is less than the second channel length.
12. The method of claim 1 , further comprising forming additional materials for the first replacement gate structure within the first RMG cavity above the interfacial gate insulation layer.
13. The method of claim 1 , further comprising forming additional materials for the second replacement gate structure within the second RMG cavity above the conformal gate insulation layer.
14. The method of claim 1 , further comprising forming a high-k gate insulation layer on and in contact with the interfacial gate insulation layer within the first RMG cavity.
15. The method of claim 1 , further comprising forming a high-k gate insulation layer on and in contact with the conformal gate insulation layer within the second RMG cavity.
16. A method of forming first and second replacement gate structures for, respectively, first and second transistor devices that are formed above a semiconductor substrate, the method comprising:
forming first and second sacrificial gate structures for, respectively, the first and second transistor devices, the first and second sacrificial gate structures comprising, respectively, first and second sacrificial gate insulation layers and, respectively, first and second sacrificial gate electrodes;
removing the first and second sacrificial gate electrodes so as to at least partially define, respectively, first and second replacement gate (RMG) cavities for, respectively, the first and second transistor devices;
removing the second sacrificial gate insulation layer from the second RMG cavity while leaving the first sacrificial gate insulation layer in position in the first RMG cavity, the removal of the second sacrificial gate insulation layer from the second RMG cavity exposing a surface of the semiconductor substrate within the second RMG cavity;
performing a conformal deposition process to form a conformal gate insulation layer in both the first and second RMG cavities, the conformal gate insulation layer being formed on and in contact with the first sacrificial gate insulation layer within the first RMG cavity and on and in contact with the exposed surface of the semiconductor substrate within the second RMG cavity;
performing at least one process operation to remove the conformal gate insulation layer and the first sacrificial gate insulation layer from the first RMG cavity while leaving the conformal gate insulation layer in position in the second RMG cavity, the removal of the first sacrificial gate insulation layer from the first RMG cavity exposing a surface of the semiconductor substrate within the first RMG cavity; and
performing an oxidation process to form an interfacial gate insulation layer only in the first RMG cavity, the interfacial gate insulation layer being formed on and in contact with the exposed surface of the semiconductor substrate within the first RMG cavity.
17. The method of claim 16 , further comprising forming additional materials for the first replacement gate structure within the first RMG cavity above the interfacial gate insulation layer.
18. The method of claim 16 , further comprising forming additional materials for the second replacement gate structure within the second RMG cavity above the conformal gate insulation layer.
19. The method of claim 16 , wherein the first transistor device has a channel length that is less than 18 nm and the second transistor device has a channel length that falls within a range of 18-30 nm.