Decision for executing full-memory refresh during memory sub-system power-on stage

1. A system comprising:

a plurality of memory devices storing a set of codewords; and

a processing device, operatively coupled to the plurality of memory devices, to:

detect a power-on of the system;

in response to detection of the power-on of the system, determine a read-retry trigger rate (TR), based on a subset of codewords stored at the plurality of memory devices, during a time interval directly after an initialization of the plurality of memory devices and one of before or at a beginning of a reduced performance time period that precedes a normal operating mode of the plurality of memory devices, wherein the reduced performance time period is a first reduced performance time period after the power-on of the system and no full-memory refresh operation is performed during the normal operating mode;

determine whether the TR satisfies a threshold criterion; and

in response to the TR not satisfying the threshold criterion, initialize the full-memory refresh operation of the plurality of memory devices.

2. The system of claim 1 , wherein, in response to the TR satisfying the threshold criterion, the processing device is further to cause the system to enter a normal operating mode without the full-memory refresh operation.

3. The system of claim 1 , wherein to satisfy the threshold criterion, the TR is to be less than a TR requirement value.

4. The system of claim 1 , wherein the TR is determined based on at least one of:

first read operations of the plurality of memory devices comprising cell refresh operations performed by the processing device; or

second read operations of the plurality of memory devices issued by a host system coupled to the system.

5. The system of claim 4 , wherein the processing device is to perform the cell refresh operations on a subset of codewords at least one of during or after a designated initialization period of the plurality of memory devices.

6. The system of claim 4 , wherein the processing device is to pass the second read operations from the host system to the plurality of memory devices during a designated reduced performance period after the initialization of the plurality of memory devices.

7. The system of claim 1 , wherein the time interval comprises a time period of less than one second.

8. A system comprising:

a plurality of memory components; and

a processing device, operatively coupled to the plurality of memory components, to:

detect a power-on of the system;

initiate, at least during a designated initialization period that follows directly after the power-on of the system, cell refresh operations on a subset of codewords stored at the plurality of memory components, the cell refresh operations comprising read operations performed on the subset of codewords;

determine a read-retry trigger rate (TR) based on the read operations performed on the subset of codewords during a time interval directly after actual initialization of the system, wherein the time interval overlaps with the designated initialization period, wherein the time interval comprises a time period before entering a normal operating mode, and no full-memory refresh operation is performed during the normal operating mode;

determine whether the TR satisfies a threshold criterion; and

in response to the TR satisfying the threshold criterion, cause the system to enter the normal operating mode without performance of the full-memory refresh operation.

9. The system of claim 8 , wherein, in response to the TR not satisfying the threshold criterion, the processing device further to initialize the full-memory refresh operation of the plurality of memory components.

10. The system of claim 8 , wherein to satisfy the threshold criterion, the TR is to be less than a TR requirement value multiplied by a scaling factor, wherein the scaling factor is less than one (“1”).

11. The system of claim 8 , wherein the TR is further determined based on second read operations of the plurality of memory components issued by a host system during a designated reduced performance period after the designated initialization period.

12. The system of claim 8 , wherein the processing device is to perform the cell refresh operations on the subset of codewords also after the designated initialization period.

13. A method comprising:

detecting, by a processing device of a memory sub-system, a power-on of the memory sub-system, wherein the memory sub-system comprises a plurality of memory devices;

determining, by the processing device in response to the detecting, a read-retry trigger rate (TR) based on a plurality of logical units stored at a plurality of memory devices during a time interval directly after initialization of the memory sub-system and one of before or at a beginning of a reduced performance time period that precedes a normal operating mode of the plurality of memory devices, wherein each logical unit comprises one or more codewords, wherein the reduced performance time period is a first reduced performance time period after the power-on of the system and no full-memory refresh operation is performed during the normal operating mode;

determining, by the processing device, whether the TR satisfies a threshold criterion; and

in response to the TR not satisfying the threshold criterion, initializing the full-memory refresh operation of the plurality of memory devices of the memory sub-system.

14. The method of claim 13 , wherein, in response to the TR satisfying the threshold criterion, the method further comprising causing the memory sub-system to enter the normal operating mode without performing the full-memory refresh operation.

15. The method of claim 13 , wherein satisfying the threshold criterion comprises the TR being less than a TR requirement value multiplied by a scaling factor, wherein the scaling factor is less than one (“1”).

16. The method of claim 13 , wherein determining the TR comprises determining the TR based on at least one of:

first read operations of the plurality of memory devices, the first read operations comprising cell refresh operations performed by the processing device; or

second read operations of the plurality of memory devices issued by a host system coupled to the memory sub-system.

17. The method of claim 16 , further comprising performing the cell refresh operations on the plurality of logic units at least one of during or after a designated initialization period of the memory sub-system.

18. The method of claim 17 , further comprising passing the second read operations from the host system to the memory sub-system during a designated reduced performance period after the designated initialization period of the memory sub-system.

19. The method of claim 13 , wherein the full-memory refresh operation is mixed with servicing memory operations received from a host system.