System for handling repeated programming errors
A system comprising a plurality of memory devices, as well as a processing device, operatively coupled with the plurality of memory devices. The processing device detects a write operation error during a write operation on a memory segment of the plurality of memory devices, wherein the memory segment comprises respective memory cells from each of the plurality of memory devices. The processing device determines that a back-to-back (B2B) count satisfies a B2B threshold criterion, wherein the B2B count corresponds to one of the plurality of memory devices. Responsive to determining that the B2B count satisfies the B2B threshold criterion, the processing device prevents, for a threshold duration of time, any subsequent write operations from being performed on the one of the plurality of memory devices, wherein a length of the threshold duration of time is determined by a period during which the B2B count continuously satisfies the B2B threshold criterion.
1 . A system comprising:
a plurality of memory devices; and
a processing device, operatively coupled with the plurality of memory devices, to perform operations comprising:
detecting a write operation error during a write operation on a memory segment of the plurality of memory devices, wherein the memory segment comprises respective memory cells from each of the plurality of memory devices;
determining that a back-to-back (B2B) count satisfies a B2B threshold criterion, wherein the B2B count corresponds to one of the plurality of memory devices; and
responsive to determining that the B2B count satisfies the B2B threshold criterion, preventing, for a threshold duration of time, any subsequent write operations from being performed on the one of the plurality of memory devices, wherein a length of the threshold duration of time is determined by a period during which the B2B count continuously satisfies the B2B threshold criterion.
2 . The system of claim 1 , wherein the B2B count comprises a number of repeated write operation errors from the one of the plurality of memory devices.
3 . The system of claim 2 , wherein the B2B count of two repeated memory segment write operation errors satisfies the B2B threshold criterion.
4 . The system of claim 2 , wherein the B2B count decreases for a successful write operation on the memory segment following the number of repeated write operation errors from the one of the plurality of memory devices.
5 . The system of claim 1 , wherein the processing device is to perform operations further comprising:
responsive to determining that the B2B count no longer satisfies the B2B threshold criterion, permitting the subsequent write operations to be performed on the one of the plurality of memory devices.
6 . The system of claim 1 , wherein the processing device is to perform operations further comprising:
determining that the memory segment satisfies a validity threshold criterion; and
responsive to determining that the memory segment satisfies the validity threshold criterion, performing a media management operation on the memory segment.
7 . The system of claim 6 , wherein performing the media management operation comprises:
performing a read operation on the memory segment;
performing a write operation on an available memory segment to write data from the memory segment, wherein the available memory segment has not been written to; and
performing an erase operation on the memory segment.
8 . The system of claim 1 , wherein preventing any subsequent write operations from being performed on the one of the plurality of memory devices comprises:
marking the respective memory cells from the one of the plurality of memory devices with a blocking marker in a metadata table.
9 . A method comprising:
detecting a write operation error during a write operation on a memory segment of a plurality of memory devices, wherein the memory segment comprises respective memory cells from each of the plurality of memory devices;
determining that a back-to-back (B2B) count satisfies a B2B threshold criterion, wherein the B2B count corresponds to one of the plurality of memory devices; and
responsive to determining that the B2B count satisfies the B2B threshold criterion, preventing, for a threshold duration of time, any subsequent write operations from being performed on the one of the plurality of memory devices, wherein a length of the threshold duration of time is determined by a period during which the B2B count continuously satisfies the B2B threshold criterion.
10 . The method of claim 9 , wherein the B2B count comprises a number of repeated write operation errors from the one of the plurality of memory devices.
11 . The method of claim 10 , wherein the B2B count of two repeated memory segment write operation errors satisfies the B2B threshold criterion.
12 . The method of claim 10 , wherein the B2B count decreases for a successful write operation on the memory segment following the number of repeated write operation errors from the one of the plurality of memory devices.
13 . The method of claim 9 , further comprising:
responsive to determining that the B2B count no longer satisfies the B2B threshold criterion, permitting the subsequent write operations to be performed on the one of the plurality of memory devices.
14 . The method of claim 9 , further comprising:
determining that the memory segment satisfies a validity threshold criterion; and
responsive to determining that the memory segment satisfies the validity threshold criterion, performing a media management operation on the memory segment.
15 . The method of claim 14 , wherein performing the media management operation comprises:
performing a read operation on the memory segment;
performing a write operation on an available memory segment to write data from the memory segment, wherein the available memory segment has not been written to; and
performing an erase operation on the memory segment.
16 . The method of claim 9 , wherein preventing any subsequent write operations from being performed on the one of the plurality of memory devices comprises:
marking the respective memory cells from the one of the plurality of memory devices with a blocking marker in a metadata table.
17 . A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:
detecting a write operation error during a write operation on a memory segment of a plurality of memory devices, wherein the memory segment comprises respective memory cells from each of the plurality of memory devices;
determining that a back-to-back (B2B) count satisfies a B2B threshold criterion, wherein the B2B count corresponds to one of the plurality of memory devices; and
responsive to determining that the B2B count satisfies the B2B threshold criterion, preventing, for a threshold duration of time, any subsequent write operations from being performed on the one of the plurality of memory devices, wherein a length of the threshold duration of time is determined by a period during which the B2B count continuously satisfies the B2B threshold criterion.
18 . The non-transitory computer-readable storage medium of claim 17 , wherein the B2B count comprises a number of repeated write operation errors from the one of the plurality of memory devices.
19 . The non-transitory computer-readable storage medium of claim 18 , wherein the B2B count of two repeated memory segment write operation errors satisfies the B2B threshold criterion.
20 . The non-transitory computer-readable storage medium of claim 18 , wherein the B2B count decreases for a successful write operation on the memory segment following the number of repeated write operation errors from the one of the plurality of memory devices.