IP Library › Granted Patent US 10,700,264
Granted Patent B2
US 10,700,264 · App. 16/511,862 · Granted Jun 30, 2020

Memory device and fabrication method thereof

Inventors: Wei-Hao Liao (Taichung, TW); Chih-Wei Lu (Hsinchu, TW); Hsi-Wen Tien (Hsinchu County, TW); Pin-Ren Dai (New Taipei, TW); Chung-Ju Lee (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
H01L43/02H01L27/228H01L43/08H01L43/12
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Quick Facts
Patent No.
US 10,700,264
App. No.
16/511,862
Granted
Jun 30, 2020
Kind
B2
Abstract

A method includes forming in sequence a bottom magnetic layer, a tunnel barrier layer, a top magnetic layer, and a top electrode layer over a bottom electrode layer; performing a first etching process to recess the top electrode layer, in which the first etching process stops before the top magnetic layer is etched; performing a second etching process to pattern the top electrode layer as a top electrode and the top magnetic layer as a patterned top magnetic layer, in which the second etching process stops before the bottom magnetic layer is etched; forming a first spacer around the top electrode and the patterned top magnetic layer; and after forming the first spacer, performing a third etching process to pattern the tunnel barrier layer as a patterned tunnel barrier layer and the bottom magnetic layer as a patterned bottom magnetic layer.

Claims (42)

1. A method, comprising:

forming in sequence a bottom magnetic layer, a tunnel barrier layer, a top magnetic layer, and a top electrode layer over a bottom electrode layer;

performing a first etching process to recess the top electrode layer, wherein the first etching process stops before the top magnetic layer is etched;

performing a second etching process to pattern the top electrode layer as a top electrode and the top magnetic layer as a patterned top magnetic layer, wherein the second etching process stops before the bottom magnetic layer is etched, and a metal residue resulting from the second etching process is re-sputtered over a sidewall of the top electrode and a sidewall of the patterned top magnetic layer;

forming a first spacer around the top electrode and the patterned top magnetic layer such that the metal residue is encapsulated by the first spacer; and

after forming the first spacer, performing a third etching process to pattern the tunnel barrier layer as a patterned tunnel barrier layer and the bottom magnetic layer as a patterned bottom magnetic layer.

2. The method of claim 1 , wherein the tunnel barrier layer has higher etch resistance to the second etching process than that of the top magnetic layer.

3. The method of claim 1 , wherein the third etching process is performed such that a metal residue resulting from the third etching process is re-sputtered over a sidewall of the patterned tunnel barrier and a sidewall of the patterned bottom magnetic layer.

4. The method of claim 3 , wherein the metal residue resulting from the second etching process and the metal residue resulting from the third etching process are made of different materials.

5. The method of claim 3 , wherein the metal residue resulting from the second etching process is separated from the metal residue resulting from the third etching process.

6. The method of claim 1 , wherein the bottom electrode layer is recessed by the third etching process.

7. The method of claim 6 , further comprising:

after performing the third etching process, forming a second spacer extending upwardly from a recessed surface of the bottom electrode layer to the top electrode.

8. A method, comprising:

forming in sequence a bottom magnetic layer, a tunnel barrier layer, and a top magnetic layer over a bottom electrode layer;

performing a first etching process to pattern the top magnetic layer as a patterned top magnetic layer;

forming a first spacer around the patterned top magnetic layer;

after forming the first spacer, performing a second etching process to pattern the tunnel barrier layer as a patterned tunnel barrier layer and the bottom magnetic layer as a patterned bottom magnetic layer, wherein the bottom electrode layer is recessed by the second etching process; and

forming a spacer layer having a first portion extending laterally along a recessed surface of the bottom electrode layer and a second portion extending upwardly from the first portion to surround the patterned top magnetic layer, the patterned tunnel barrier layer, and the patterned bottom magnetic layer.

9. The method of claim 8 , further comprising:

prior to performing the first etching process, forming a top electrode layer over the top magnetic layer and a hard mask over the top electrode layer,

wherein the first etching process is performed such that the top electrode layer is patterned as a top electrode below the hard mask, and the second etching process is performed such that the hard mask is removed from the top electrode.

10. The method of claim 8 , further comprising:

removing the first portion of the spacer layer from the recessed surface of the bottom electrode layer.

11. The method of claim 8 , wherein the first etching process is performed such that a metal material is dislodged from the top magnetic layer and re-sputtered onto a sidewall of the patterned top magnetic layer.

12. The method of claim 8 , the second etching process is performed such that metal materials are dislodged from the bottom magnetic layer and the bottom electrode layer and re-sputtered onto the patterned tunnel barrier layer, the patterned top magnetic layer, the recessed bottom electrode layer, or combinations thereof.

13. The method of claim 8 , wherein the second etching process stops before reaching a bottom surface of the bottom electrode layer.

14. The method of claim 8 , further comprising forming a top electrode layer over the top magnetic layer prior to performing the first etching process.

15. A method, comprising:

forming in sequence a bottom magnetic layer, a tunnel barrier layer, and a top magnetic layer over a bottom electrode layer;

performing a first etching process to pattern the top magnetic layer as a patterned top magnetic layer;

forming a first spacer around the patterned top magnetic layer;

after forming the first spacer, performing a second etching process to pattern the tunnel barrier layer as a patterned tunnel barrier layer and the bottom magnetic layer as a patterned bottom magnetic layer, wherein the second etching process is performed such that the bottom electrode layer has a sidewall coterminous with a sidewall of the patterned bottom magnetic layer;

forming a second spacer around the sidewall of the bottom electrode layer; and

after forming the second spacer, patterning the bottom electrode layer as a bottom electrode.

16. The method of claim 15 , further comprising:

prior to performing the first etching process, forming a top electrode layer over the top magnetic layer; and

performing a third etching process to recess the top electrode layer, wherein the top magnetic layer remains covered by the recessed top electrode layer after performing the third etching process.

17. The method of claim 16 , wherein the first etching process further patterns the recessed top electrode layer as a top electrode.

18. The method of claim 15 , wherein the first etching process and the second etching process use different etchants.

19. The method of claim 15 , wherein a width of the patterned top magnetic layer is less than a width of the patterned tunnel barrier layer.

20. The method of claim 15 , further comprising forming an interlayer dielectric over the patterned top magnetic layer, the patterned tunnel barrier layer, the patterned bottom magnetic layer, and the bottom electrode.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 17, 2019
From: LIAO, WEI-HAO; LU, CHIH-WEI; TIEN, HSI-WEN; DAI, PIN-REN; LEE, CHUNG-JU
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 049776/0113 →
Continuity (2)
Division 15811405 · Nov 13, 2017
Related Publication 20190341543A1 · Nov 7, 2019
Cited By (2)
US 12,538,714 US 12,727,167