IP Library › Granted Patent US 12,727,167
Granted Patent B2
US 12,727,167 · App. 18/355,813 · Granted Sep 1, 2026

Dielectric isolation for MRAM array

Inventors: Oscar van der Straten (Guilderland Center, NY); Koichi Motoyama (Clifton Park, NY); Chih-Chao Yang (Glenmont, NY)
Assignee: International Business Machines Corporation
H10B61/00H10N50/01H10N50/10H10N50/20H10N50/80
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Quick Facts
Patent No.
US 12,727,167
App. No.
18/355,813
Granted
Sep 1, 2026
Kind
B2
Abstract

A magnetoresistive random access memory (MRAM) includes a pillar structure having a bottom electrode, a magnetic tunnel junction (MTJ) and a top electrode disposed on the MTJ. The MTJ has a reference layer, a free layer and a tunnel barrier disposed between the reference layer and the free layer. The MTJ is disposed on the bottom electrode. The bottom electrode and the top electrode are recessed within a periphery of the MTJ to form a disrupted sidewall profile.

Claims (45)

1 . A magnetoresistive random access memory (MRAM), comprising:

a pillar structure having:

a bottom electrode;

a magnetic tunnel junction (MTJ) having a reference layer, a free layer and a tunnel barrier disposed between the reference layer and the free layer, the MTJ disposed on the bottom electrode; and

a top electrode disposed on the MTJ;

wherein the bottom electrode and the top electrode are recessed within a periphery of the MTJ to form a disrupted sidewall profile, and wherein the top electrode, tunnel barrier and bottom electrode share a same footprint.

2 . The MRAM as recited in claim 1 , further comprising a dielectric ring disposed about a periphery of the tunnel barrier, the dielectric ring extending in a same plane as the tunnel barrier to a periphery of the reference layer and the free layer.

3 . The MRAM as recited in claim 2 , wherein the dielectric ring includes silicon nitride.

4 . The MRAM as recited in claim 2 , wherein the dielectric ring includes aluminum oxide.

5 . The MRAM as recited in claim 2 , wherein the dielectric ring includes tantalum oxide.

6 . The MRAM as recited in claim 1 , further comprising an interlevel dielectric layer adjacent to the pillar structure, the interlevel dielectric layer including at least three sublayers formed by separate processes.

7 . The MRAM as recited in claim 6 , wherein the at least three sublayers includes four sublayers.

8 . The MRAM as recited in claim 6 , wherein the at least three sublayers include at least two different materials.

9 . A method for making a magnetoresistive random access memory (MRAM), comprising:

forming a bottom electrode having a first footprint;

forming a first sublayer of an interlevel dielectric layer corresponding to a level of the bottom electrode;

forming a first ferromagnetic layer on the bottom electrode having a second footprint that is larger than the first footprint;

forming a second sublayer of the interlevel dielectric layer corresponding to a level of the first ferromagnetic layer;

forming a tunnel barrier on the first ferromagnetic layer within the first footprint;

forming a dielectric ring in a plane of the tunnel barrier and extending between the first footprint and the second footprint;

forming a second ferromagnetic layer on the tunnel barrier and the dielectric ring, the second ferromagnetic layer having the second footprint;

forming a third sublayer of the interlevel dielectric layer corresponding to a level of the second ferromagnetic layer; and

forming a top electrode having the first footprint.

10 . The method as recited in claim 9 , further comprising forming a fourth sublayer of the interlevel dielectric layer corresponding to a level of the top electrode.

11 . The method as recited in claim 9 , wherein forming the first ferromagnetic layer includes forming a first portion of a sidewall spacer on sidewalls of the first ferromagnetic layer.

12 . The method as recited in claim 11 , wherein forming the second ferromagnetic layer includes forming a second portion of a sidewall spacer on sidewalls of the second ferromagnetic layer.

13 . The method as recited in claim 12 , wherein the first portion of the sidewall spacer and the second portion of the sidewall spacer intersect at the dielectric ring.

14 . The method as recited in claim 9 , wherein the dielectric ring includes silicon nitride.

15 . The method as recited in claim 9 , wherein the dielectric ring includes aluminum oxide.

16 . The method as recited in claim 9 , wherein the dielectric ring includes tantalum oxide.

17 . A method for making a magnetoresistive random access memory (MRAM), comprising:

forming a bottom electrode having a first footprint;

forming a first sublayer of an interlevel dielectric layer corresponding to a level of the bottom electrode;

forming a first ferromagnetic layer on the bottom electrode having a second footprint that is larger than the first footprint;

forming a first portion of a sidewall spacer on sidewalls of the first ferromagnetic layer;

forming a second sublayer of the interlevel dielectric layer corresponding to a level of the first ferromagnetic layer;

forming a tunnel barrier on the first ferromagnetic layer within the first footprint;

forming a dielectric ring in a plane of the tunnel barrier and extending between the first footprint and the second footprint;

forming a second ferromagnetic layer on the tunnel barrier and the dielectric ring, the second ferromagnetic layer having the second footprint;

forming a second portion of a sidewall spacer on sidewalls of the second ferromagnetic layer, wherein the first portion of the sidewall spacer and the second portion of the sidewall spacer intersect at the dielectric ring;

forming a third sublayer of the interlevel dielectric layer corresponding to a level of the second ferromagnetic layer;

forming a top electrode having the first footprint; and

forming a fourth sublayer of the interlevel dielectric layer corresponding to a level of the top electrode.

18 . The method as recited in claim 17 , wherein the dielectric ring includes aluminum oxide.

19 . The method as recited in claim 17 , wherein the dielectric ring includes tantalum oxide.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 20, 2023
From: VAN DER STRATEN, OSCAR; MOTOYAMA, KOICHI; YANG, CHIH-CHAO
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 064328/0175 →
Continuity (1)
Related Publication 20250031382A1 · Jan 23, 2025
References Cited (14)
US 8455965B2 · Li et al. · 2013 [cited by applicant]
US 8644063B2 · Li et al. · 2014 [cited by applicant]
US 9570670B2 · Park · 2017 [cited by examiner]
US 10010924B2 · Moriya · 2018 [cited by examiner]
US 10032981B2 · Han et al. · 2018 [cited by applicant]
US 10700264B2 · Liao et al. · 2020 [cited by applicant]
US 10727272B2 · Chuang et al. · 2020 [cited by applicant]
US 11114606B2 · Reznicek et al. · 2021 [cited by applicant]
US 11133457B2 · Patlolla et al. · 2021 [cited by applicant]
US 12382840B2 · Motoyama · 2025 [cited by examiner]
US 20150056722A1 · Li et al. · 2015 [cited by applicant]
US 20210098685A1 · Liou · 2021 [cited by examiner]
US 20240188448A1 · van der Straten · 2024 [cited by examiner]
US 20250107452A1 · van der Straten · 2025 [cited by examiner]