Semiconductor device including trimmed-gates

1. A semiconductor device comprising:

active regions arranged in a first grid oriented substantially parallel to a first direction; and

gate electrodes arranged spaced apart in a second grid and overlying corresponding ones of the active regions, the second grid being oriented substantially parallel to a second direction, the second direction being substantially orthogonal to the first direction;

wherein first gaps are interspersed correspondingly between neighboring ones of the active regions; and

wherein, for a flyover intersection at which a corresponding gate electrode crosses over a corresponding active region and for which the gate electrode is not functionally connected to the corresponding active region, the gate electrode does not extend substantially beyond the corresponding active region and so does not extend substantially into a corresponding one of the first gaps.

2. The semiconductor device of claim 1 , wherein:

for a functional intersection at which a corresponding gate electrode crosses over a corresponding active region and for which the gate electrode is functionally connected to the active region, an extension of the gate electrode extends a predetermined distance in the second direction beyond the corresponding active region and into the corresponding one of the first gaps.

3. The semiconductor device of claim 2 , wherein:

a height H EXT in the second direction of the extension of the gate electrode is less than or equal to about a three times multiple of a width W G in the first direction of the gate electrode, wherein:

H EXT ≤(≈3 W G ).

4. The semiconductor device of claim 1 , wherein:

the active region is configured for finFET technology.

5. A semiconductor device comprising:

active regions arranged in a first grid oriented substantially parallel to a first direction;

a first set of gate electrodes arranged spaced apart in a second grid and overlying corresponding ones of the active regions, the second grid being oriented substantially parallel to a second direction, the second direction being substantially orthogonal to the first direction;

first gaps being interspersed correspondingly between neighboring ones of the active regions;

a first subset of the set of gate electrodes, each gate electrode of the first subset being configured to extend beyond a corresponding one of the active regions a predetermined distance into a corresponding one of the first gaps in the second direction; and

a second subset of the set of gate electrodes, each gate electrode of the second subset being configured to not extend, in the second direction, substantially beyond a corresponding one of the active regions and so does not extend substantially into a corresponding one of the first gaps.

6. The semiconductor device of claim 5 , wherein:

gate electrodes of the first subset are functionally connected with corresponding ones of the active regions.

7. The semiconductor device of claim 5 , wherein:

gate electrodes of the second subset are not functionally connected with corresponding ones of the active regions.

8. The semiconductor device of claim 5 , wherein:

the predetermined distance is H EXT and is less than or equal to about a three times multiple of a width W G in the first direction of the first set of gate electrodes, wherein:

H EXT ≤(≈3 W G ).

9. The semiconductor device of claim 5 further comprising:

at least one component of a circuit positioned within one or more of the first gaps.

10. The semiconductor device of claim 9 , wherein:

gate electrodes of the first subset do not extend to the at least one component of the circuit.

11. The semiconductor device of claim 5 , wherein:

the active regions are configured for finFET technology.

12. A semiconductor device comprising:

active regions arranged in a first grid oriented substantially parallel to a first direction;

a set of gate electrodes arranged spaced apart in a second grid and overlying corresponding ones of the active regions, the second grid being oriented substantially parallel to a second direction, the second direction being substantially orthogonal to the first direction; and

a gap region interspersed between neighboring ones of the active regions in the second direction; and

wherein, for a first subset of the set of gate electrodes, each gate electrode of the first subset is configured to extend unilaterally beyond a corresponding one of the active regions but not into the gap region.

13. The semiconductor device of claim 12 , wherein:

for a second subset of the set of gate electrodes, each gate electrode of the second subset is configured to have one end extending, relative to the second direction, a predetermined distance into the gap region beyond a corresponding one of the active regions.

14. The semiconductor device of claim 13 , wherein:

gate electrodes of the second subset form functional intersections with corresponding ones of the active regions.

15. The semiconductor device of claim 13 , wherein:

a width in the first direction of each gate electrode of the second subset is greater than or equal to about one third of the predetermined distance.

16. The semiconductor device of claim 13 further comprising:

at least one component of a circuit positioned within the gap region.

17. The semiconductor device of claim 12 , wherein:

gate electrodes of the first subset form flyover intersections with corresponding ones of the active regions.

18. The semiconductor device of claim 12 , wherein:

for a second subset of the set of gate electrodes, each gate electrode of the second subset is configured to extend substantially bilaterally beyond a corresponding one of the active regions including extending substantially into the gap region.

19. The semiconductor device of claim 12 , wherein:

long axes of the active regions extend substantially in the first direction.

20. The semiconductor device of claim 12 , wherein:

the active regions are configured correspondingly for PMOS technology or NMOS technology.