IP Library Granted Patent US 10,772,206
Granted Patent B2
US 10,772,206 · App. 16/513,004 · Granted Sep 8, 2020

Board to board interconnect

Inventors: Chee Ling Wong (Sungai Ara, MY); Wil Choon Song (Bayan Lepas, MY); Khang Choong Yong (Puchong, MY); Eng Huat Goh (Ayer Itam, MY); Mohd Muhaiyiddin Bin Abdullah (Kepala Batas, MY); Tin Poay Chuah (Bayan Baru, MY)
Assignee: Intel Corporation
H05K1/117H05K1/142H05K1/0298H05K2201/09845
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Quick Facts
Patent No.
US 10,772,206
App. No.
16/513,004
Granted
Sep 8, 2020
Kind
B2
Abstract

A system for board-to-board interconnect is described herein. The system includes a first printed circuit board (PCB) having a first recess along a first edge of the first PCB that exposes a first solder pad on a layer of the first PCB. The system also includes a second PCB having a second recess along a second edge of the second PCB that exposes a second solder pad on a layer of the second PCB. The second recess is complementary to the first recess to allow the first PCB to mate with the second PCB. The first solder pad is aligned with the second solder pad when the first PCB is mated with the second PCB. The system additionally includes an assembly configured to electronically couple the first solder pad with the second solder pad.

Claims (11)

1. A system, comprising:

a first printed circuit board (PCB) having a first recess along a first edge of the first PCB, wherein the first recess includes a first solder pad exposed on a first layer of the first PCB and a second solder pad exposed on a second layer of the first PCB; wherein the first solder pad and the second solder pad being vertically and horizontally displaced from one another;

a second PCB having a second recess along a second edge of the second PCB, wherein the second recess is complementary to the first recess, and the second recess includes a third solder pad exposed on a third layer of the second PCB, and a fourth solder pad exposed on a fourth layer of the second PCB; wherein the third solder pad and the fourth solder pad being vertically and horizontally displaced from one another; and

a removable clamp to couple together the first PCB to the second PCB;

wherein:

the first solder pad is electrically coupled to the third solder pad on the third layer of the second PCB by at least a metallized particle interconnect, with the first solder pad aligned with the third solder pad on the third layer of the second PCB;

the second solder pad is electrically coupled to the fourth solder pad on the fourth layer of the second PCB by at least a metallized particle interconnect, with the second solder pad aligned with the fourth solder pad on the fourth layer of the second PCB; and

a z-height of the first PCB, a z-height of the second PCB and a z-height of the first PCB and the second PCB when coupled together are substantially equal.

2. The system of claim 1 , wherein the first PCB is a system in package (SIP) and the second PCB is an IO board.

3. The system of claim 2 , wherein the IO board includes a cavity to house the first PCB.

4. The system of claim 1 , wherein the metallized particle interconnect includes a conductive material comprising an elastomer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 27, 2020
From: WONG, CHEE LING; SONG, WIL CHOON; YONG, KHANG CHOONG; GOH, ENG HUAT; ABDULLAH, MOHD MUHAIYIDDIN BIN; CHUAH, TIN POAY
To: INTEL CORPORATION
Reel/Frame 053320/0638 →
Continuity (2)
Continuation 14757984 · Dec 26, 2015
Related Publication 20190342996A1 · Nov 7, 2019