Insulated gated field effect transistor structure having shielded source and method
A semiconductor device includes a region of semiconductor material comprising a semiconductor layer of a first conductivity type and having a first major surface. A body region of a second conductivity type opposite to the first conductivity type is disposed in the second semiconductor layer extending from the first major surface. The body region comprises a first segment having a first doping concentration, and a second segment laterally adjacent to the first segment and adjacent to the first major surface having a second doping concentration less than the first doping concentration. A source region of the first conductivity type is disposed in the first segment but is not disposed in at least a portion of the second segment. An insulated gate electrode is disposed adjacent to the region of semiconductor material adjoining the first segment, the second segment, and the source region. A conductive layer is electrically connected to the first segment, the second segment, and the first source region. During a linear mode of operation, current flows first in the second segment but not in the first segment to reduce the likelihood of thermal runaway.
1. A semiconductor device structure, comprising:
a region of semiconductor material comprising a first semiconductor layer of a first conductivity type and having a first major surface;
a first body region of a second conductivity type opposite to the first conductivity type disposed in the first semiconductor layer extending from the first major surface, wherein the first body region comprises:
a first segment having a first doping concentration; and
a second segment laterally adjacent to the first segment and adjacent to the first major surface having a second doping concentration less than the first doping concentration;
a first source region of the first conductivity type disposed in the first segment of the body region but not disposed in at least a portion of the second segment;
an insulated gate electrode disposed adjacent to the region of semiconductor material adjoining the first segment and configured to provide a first channel region in the first segment, adjoining the second segment and configured to provide a second channel region in the second segment, and adjoining the first source region;
a first conductive layer electrically connected to the first segment, the second segment, and the first source region; and
a second conductive layer adjacent to a second major surface of the region of semiconductor material opposite to the first major surface.
2. The semiconductor device structure of claim 1 , further comprising:
a ballast resistor structure electrically connected to the first source region, wherein the ballast resistor structure does not physically contact the first conductive layer.
3. The semiconductor device structure of claim 2 , wherein:
the ballast resistor structure comprises a doped region of the first conductivity type disposed within the first body region; and
the doped region is disposed within the second segment and laterally extends to overlap a portion of the first segment.
4. The semiconductor device structure of claim 1 , wherein:
the first segment extends into the first semiconductor layer to a first depth; and
the second segment extends into the first semiconductor layer to a second depth.
5. The semiconductor device structure of claim 4 , wherein:
the first depth is greater than the second depth.
6. The semiconductor device structure of claim 1 , wherein:
the first body region comprises a first stripe region; and
the semiconductor device structure further comprises:
a second body region comprising:
a second stripe region generally parallel to the first stripe region;
a second body region first segment having the first doping concentration; and
a second body region second segment having the second doping concentration; and
a second source region of the first conductivity type disposed within the second body region first segment and laterally offset with respect to the first source region.
7. The semiconductor device structure of claim 6 , wherein:
the first segment of the first body region has a first width; and
the second body region first segment has a second width different than the first width.
8. The semiconductor device structure of claim 7 , wherein:
the second width is less than the first width.
9. The semiconductor device structure of claim 1 , wherein:
the first body region comprises a third segment laterally interposed between the first segment and the second segment;
the third segment comprises a third doping concentration between the first doping concentration and the second doping concentration; and
the first source region laterally extends into at least a portion of the third segment.
10. The semiconductor device structure of claim 1 , wherein:
the first doping concentration has a first peak dopant concentration;
the second doping concentration has a second peak dopant concentration; and
the first peak dopant concentration is about twice the second peak dopant concentration.
11. A semiconductor device structure, comprising:
a region of semiconductor material comprising a first semiconductor layer of a first conductivity type and having a first major surface;
a first body region of a second conductivity type opposite to the first conductivity type disposed in the first semiconductor layer extending from the first major surface, wherein the first body region comprises:
a first body region first segment having a first doping concentration; and
a first body region second segment laterally adjacent to the first body region first segment and adjacent to the first major surface having a second doping concentration less than the first doping concentration;
a first source region of the first conductivity type disposed in the first body region first segment but not disposed in at least a portion of the first body region second segment;
an insulated gate electrode disposed adjacent to the region of semiconductor material adjoining the first body region first segment, the first body region second segment, and the first source region;
a first conductive layer disposed in a contact trench and electrically connected to the first body region first segment, the first body region second segment, and the first source region; and
a ballast resistor structure electrically connected to the first source region, wherein the ballast resistor structure does not physically contact the first conductive layer.
12. The semiconductor device structure of claim 11 ,
wherein the ballast resistor structure comprises:
a doped region of the first conductivity type disposed within the first body region second segment and laterally extends to overlap a portion of the first body region first segment.
13. The semiconductor device structure of claim 11 , wherein:
the first body region first segment extends into the first semiconductor layer to a first depth; and
the first body region second segment extends into the first semiconductor layer to a second depth that is different than the first depth.
14. The semiconductor device structure of claim 11 , wherein:
the first body region comprises a first stripe region; and
the semiconductor device structure further comprises:
a second body region comprising:
a second stripe region generally parallel to the first stripe region;
a second body region first segment having the first doping concentration; and
a second body region second segment having the second doped concentration; and
a second source region of the first conductivity type disposed within the second body region first segment and laterally offset with respect to the first source region.
15. The semiconductor device structure of claim 14 , wherein:
the first body region first segment has a first width; and
the second body region first segment has a second width different than the first width.
16. The semiconductor device structure of claim 11 , wherein:
the first doping concentration has a first peak dopant concentration;
the second doping concentration has a second peak dopant concentration; and
the first peak dopant concentration is about twice the second peak dopant concentration.
17. A method of forming a semiconductor device structure, comprising:
providing a region of semiconductor material comprising a first semiconductor layer of a first conductivity type and having a first major surface;
providing a first body region of a second conductivity type opposite to the first conductivity type disposed in the first semiconductor layer extending from the first major surface, wherein the first body region comprises:
a first body region first segment having a first doping concentration; and
a first body region second segment laterally adjacent to the first body region first segment and adjacent to the first major surface having a second doping concentration less than the first doping concentration;
providing a first source region of the first conductivity type disposed in the first body region first segment but not disposed in at least a portion of the first body region second segment;
providing an insulated gate electrode disposed within the region of semiconductor material adjoining the first body region first segment and configured to provide a first channel region in the first segment, adjoining the first body region second segment and configured to provide a second channel region in the second segment, and adjoining the first source region; and
providing a first conductive layer disposed in a contact trench and electrically connected to the first body region first segment, the first body region second segment, and the first source region.
18. The method of claim 17 , further comprising:
providing a ballast resistor structure electrically connected to the first source region, wherein:
the ballast resistor structure does not physically contact the first conductive layer; and
the ballast resistor structure comprises:
a doped region of the first conductivity type disposed within the first body region second segment and laterally extends to overlap a portion of the first body region first segment.
19. The method of claim 17 , wherein:
providing the first body region comprises a providing first stripe region; and
the method further comprises:
providing a second body region comprising:
a second stripe region generally parallel to the first stripe region;
a second body region first segment having the first doping concentration; and
a second body region second segment having the second doped concentration; and
providing a second source region of the first conductivity type disposed within the second body region first segment and laterally offset with respect to the first source region.
20. The method of claim 19 , wherein:
providing the first body region comprises providing the first body region first segment having a first width; and
providing the second body region comprises providing the second body region first segment having a second width different than the first width.