Gate driver and electroluminescence display device using the same
An electroluminescence display device and a gate driver are provided. An electroluminescence display device includes: an emission line (EL), subpixels connected to the EL, and an emission driver supplying an emission signal to the EL, the emission driver including a plurality of stages, a k th stage including: a first output (O 1 ) node connected to the EL, a second output (O 2 ) node, a Q node, a pull-down circuit and a pull-up circuit respectively controlled by the Q and O 2 nodes and providing a voltage to the O 1 node, a first controller receiving an O 1 node voltage of a (k−1) th stage or a first start signal, a second controller receiving an O 2 node voltage of the (k−1) th stage or a second start signal, a third controller controlling the O 2 node voltage, and a fourth controller controlled by the O 2 node, wherein ‘k’ is a natural number ≥1.
1. An electroluminescence display device, comprising:
an emission line;
subpixels connected to the emission line; and
a gate driver configured to supply an emission signal to the emission line, the gate driver comprising a plurality of stages,
wherein a k th stage, among the plurality of stages, comprises:
a first output node connected to the emission line;
a second output node;
a Q node connected to a first controller and a pull-down circuit;
the pull-down circuit and a pull-up circuit respectively controlled by the Q node and the second output node, the pull-down circuit and the pull-up circuit being configured to provide a voltage to the first output node;
the first controller configured to receive a voltage of a first output node of a (k-1) th stage, among the plurality of stages, or a first start signal;
a second controller configured to receive a voltage of a second output node of the (k-1) th stage or a second start signal;
a third controller configured to control the voltage of the second output node; and
a fourth controller configured to:
be controlled by the second output node, and
control the voltage of the first output node,
wherein the fourth controller comprises a Q node stabilizer configured to reduce parasitic capacitance formed in the Q node,
wherein the Q node stabilizer is connected to the pull-down circuit via the Q node,
wherein the Q node stabilizer is connected to the first controller via a Q′-node,
wherein ‘k’ is a natural number of 1 or more,
wherein the third controller comprises:
a T 3 transistor configured to be controlled by the Q node,
a T 4 transistor configured to be controlled by a first clock signal,
a T 5 transistor configured to be controlled by a QB node, and
a first capacitor comprising:
a first electrode connected to the second controller, and
a second electrode connected to the second output node,
wherein one electrode of the T 3 transistor and a first electrode of the T 4 transistor are connected to the second electrode of the first capacitor, and
wherein a second electrode of the T 4 transistor is connected to a first electrode of the T 5 transistor.
2. The electroluminescence display device of claim 1 , wherein the fourth controller further comprises an operation margin enhancement portion configured to reduce or prevent collision between a plurality of voltages of the fourth controller.
3. The electroluminescence display device of claim 1 , wherein:
at least one transistor connected to the first capacitor is in the fourth controller, the at least one transistor being a double-gate type transistor;
the second electrode of the first capacitor is connected to:
a gate electrode of the transistor in the fourth controller; and
the first electrode of the T 4 transistor in the third controller; and
the first electrode of the first capacitor is connected to the second controller.
4. The electroluminescence display device of claim 1 , wherein the pull-down circuit comprises a capacitor connected to the Q node and the first output node.
5. The electroluminescence display device of claim 1 , wherein:
the first controller is further configured to be controlled by a first clock signal;
the second controller is further configured to be controlled by a second clock signal; and
the first clock signal and the second clock signal swing between a low voltage and a high voltage at a cycle of one horizontal period and have their respective phases opposite to each other.
6. The electroluminescence display device of claim 1 , wherein the fourth controller comprises:
a T 6 transistor configured to be controlled by the second output node and connected to the Q node;
a T 9 transistor connected to:
the pull-down circuit via the Q node; and
the first controller via the Q′-node; and
a C 2 capacitor connected to the Q node and a second clock signal line,
wherein:
a gate electrode of the T 9 transistor is connected to a low voltage and a source electrode, or
a drain electrode of the T 9 transistor is connected to the Q node.
7. The electroluminescence display device of claim 6 , wherein:
the fourth controller further comprises:
a T 10 transistor configured to be controlled by a second clock signal and connected to the Q′-node and the T 6 transistor; and
a C 4 capacitor connected to the second output node and the high voltage line,
wherein:
a gate electrode of the T 10 transistor is connected to the second clock signal line and a source electrode, or
a drain electrode of the T 10 transistor is connected to the Q′-node and a drain electrode or a source electrode of the T 6 transistor.