Gate driver circuit, display panel and display device including the same
The disclosure relates to a display panel, a display device, and a gate driver circuit. According to an embodiment, a display panel includes a gate driver circuit in which when a display device operates at low-speed for a long time, a voltage of a Q node between an input and an output of a gate shift register in a gate driver circuit does not rise but is maintained at a value below a certain voltage. Here, potential maintaining circuit (PMC) is connected to a Q node, a Q2 node, or a vulnerable node between an input unit and an output unit of the gate shift register. The PMC maintains a potential of the Q node at a value below a selected level during a light-emitting operation for display. Thus, image quality defect due to damage to output voltage resulting from leakage and noise at an output node is prevented.
1. A display panel, comprising:
multiple stages selectively connected to lines to which multiple clock signals are supplied, wherein the multiple stages are configured to sequentially output a scan pulse,
wherein each of the multiple stages includes:
an input unit electrically connected to each of a start signal line and a clock signal line;
a Q node controller electrically connected to the input unit through a Q2 node;
an output unit electrically connected to the Q node controller through a Q node;
a voltage potential maintaining circuit electrically connected to the Q node; and
a QB node controller having one side electrically connected to the output unit through a QB node and the other side electrically connected to the output unit through a gate-off signal line,
wherein the voltage potential maintaining circuit is configured to operate based on a driving signal and maintains a voltage potential of the Q node at a value below a selected level,
wherein the output unit includes:
a pull-up transistor for outputting the scan signal to an output terminal based on a voltage level of the Q node; and
a pull-down transistor for supplying a gate-off signal to the output terminal based on a voltage level of the QB node,
wherein the pull-up transistor includes a first thin-film transistor having a gate electrode electrically connected to the Q node, a first electrode electrically connected to a gate-on signal line, and a second electrode electrically connected to the output terminal,
wherein the pull-down transistor includes a second thin-film transistor having a gate electrode electrically connected to the QB node, a first electrode electrically connected to the output terminal, and a second electrode electrically connected to the gate-off signal line.
2. The display panel of claim 1 , wherein a first capacitor is electrically connected to and disposed between the Q node to which the gate electrode of the first thin-film transistor is electrically connected and the output terminal to which the second electrode of the first thin-film transistor is electrically connected.
3. The display panel of claim 1 , wherein the voltage potential maintaining circuit includes:
a seventh thin-film transistor having a gate electrode electrically connected to a driving signal line, a first electrode electrically connected to a low signal line, and a second electrode electrically connected to a contact point between the Q node and the first capacitor;
a diode electrically connected to and disposed between the contact point between the Q node and the first capacitor and the second electrode of the seventh thin-film transistor; and
a second capacitor electrically connected to the second electrode of the seventh thin-film transistor, wherein an application signal line is electrically connected to the second electrode of the seventh thin-film transistor through the second capacitor.
4. The display panel of claim 1 , wherein the input unit includes a third thin-film transistor having a gate electrode electrically connected to the clock signal line, a first electrode electrically connected to the start signal line, and a second electrode electrically connected to the Q2 node.
5. A display panel, comprising:
multiple stages selectively connected to lines to which multiple clock signals are supplied, wherein the multiple stages are configured to sequentially output a scan pulse,
wherein each of the multiple stages includes:
an input unit electrically connected to each of a start signal line and a clock signal line;
a Q node controller electrically connected to the input unit through a Q2 node;
an output unit electrically connected to the Q node controller through a Q node;
a voltage potential maintaining circuit electrically connected to the Q node; and
a QB node controller having one side electrically connected to the output unit through a QB node and the other side electrically connected to the output unit through a gate-off signal line,
wherein the voltage potential maintaining circuit is configured to operate based on a driving signal and maintains a voltage potential of the Q node at a value below a selected level,
wherein the Q node controller includes a TFT active-Anti-backflow (TA) thin-film transistor having a gate electrode electrically connected to a gate-on signal line, a first electrode electrically connected to the Q node, and a second electrode electrically connected to the Q2 node.
6. A display panel, comprising:
multiple stages selectively connected to lines to which multiple clock signals are supplied, wherein the multiple stages are configured to sequentially output a scan pulse,
wherein each of the multiple stages includes:
an input unit electrically connected to each of a start signal line and a clock signal line;
a Q node controller electrically connected to the input unit through a Q2 node;
an output unit electrically connected to the Q node controller through a Q node;
a voltage potential maintaining circuit electrically connected to the Q node; and
a QB node controller having one side electrically connected to the output unit through a QB node and the other side electrically connected to the output unit through a gate-off signal line,
wherein the voltage potential maintaining circuit is configured to operate based on a driving signal and maintains a voltage potential of the Q node at a value below a selected level,
wherein the QB node controller includes:
a fifth thin-film transistor having a first electrode electrically connected to the clock signal line, a gate electrode electrically connected to the clock signal line through a third capacitor, and a second electrode electrically connected to the QB node;
a fourth thin-film transistor having a gate electrode electrically connected to the start signal line, a first electrode electrically connected to the gate electrode of the fifth thin-film transistor, and a second electrode electrically connected to the output unit through the gate-off signal line; and
a sixth thin-film transistor having a gate electrode electrically connected to the Q2 node, a first electrode electrically connected to the QB node, and a second electrode electrically connected to the output unit through the gate-off signal line.