Gate driver and display panel having the same
A display panel includes pixels connected to gate lines, and a gate driver that supplies a gate signal to at least one of the gate lines and includes a plurality of stages. Each stage includes a pull-up transistor to apply a turn-on voltage of a first clock signal to an output terminal responsive to a voltage at a Q-node, a pull-down transistor to apply a turn-off voltage to the output terminal responsive to a voltage at a QB-node that holds the turn-on voltage during a period in which the output terminal is applied the turn-off voltage, and a QB-node control unit to apply the turn-on voltage to the QB-node responsive to the first clock signal and a second clock signal in reverse-phase with the first clock signal. Accordingly, a display panel may include a gate driver that can set, reset, and hold the voltage at a QB-node.
1 . A gate driver, comprising:
a QB-node control circuit configured to control a QB-node, the QB-node being a gate node of a pull-down transistor, the QB-node control circuit comprising:
a first transistor having a gate electrode connected to a start signal input terminal, a first electrode connected to a QP-node for controlling the QB-node, and a second electrode connected to a gate-off voltage input terminal;
a second transistor having a gate electrode connected to a first clock input terminal, a first electrode connected to the QP-node, and a second electrode connected to an output terminal connected between the pull-down transistor and a pull-up transistor;
a third transistor configured to apply a gate-off voltage to the QB-node;
a fourth transistor having a gate electrode connected to the QP-node, a first electrode connected to the QB-node, and a second electrode connected to a second clock input terminal; and
a first capacitor connected between the QP-node and the second clock input terminal; and
a fifth transistor having a gate electrode directly connected to the start signal input terminal and to the gate electrode of the first transistor, a first electrode connected to a Q1-node for controlling the pull-up transistor, and a second electrode connected to the start signal input terminal.
2 . The gate driver of claim 1 ,
wherein the third transistor has a gate electrode connected to the start signal input terminal, a first electrode connected to the QB-node, and a second electrode connected to the gate-off voltage input terminal.
3 . The gate driver of claim 1 ,
wherein the QB-node control circuit further comprises a second capacitor connected between the QB-node and the gate-off voltage input terminal, and
wherein the QB-node is configured to be at the gate-off voltage during a first period and a second period.
4 . The gate driver of claim 1 , further comprising:
a seventh transistor having a gate electrode connected to a gate-on voltage input terminal, a first electrode connected to the pull-up transistor, and a second electrode connected to the fifth transistor.
5 . The gate driver of claim 1 , further comprising:
a sixth transistor having a gate electrode connected to the QB-node, a first electrode connected to the Q1-node for controlling the pull-up transistor, and a second electrode connected to the gate-off voltage input terminal.
6 . The gate driver of claim 1 ,
wherein the first transistor is turned on, such that the gate-off voltage is applied to the QP-node, and the third transistor is turned on, such that the gate-off voltage is applied to the QB-node, while a start signal is a gate-on voltage.
7 . A gate driver, comprising:
a plurality of cascading stages configured to generate a plurality of scan signals, respectively, each of the plurality of stages comprising:
a first transistor configured to apply a gate-off voltage to a QP-node for controlling a QB-node;
a second transistor having a gate electrode connected to a first clock input terminal, a first electrode connected to the QP-node, and a second electrode connected to an output terminal connected between a pull-down transistor and a pull-up transistor;
a third transistor having a gate electrode directly connected to a Q1-node for controlling the pull-up transistor, a first electrode connected to the QB-node, and a second electrode connected to a gate-off voltage input terminal;
a fourth transistor having a gate electrode connected to the QP-node, a first electrode connected to the QB-node, and a second electrode connected to a second clock input terminal; and
a fifth transistor having a gate electrode connected to the second clock input terminal, a first electrode connected to the Q1-node, and a second electrode connected to a start signal input terminal.
8 . The gate driver of claim 7 ,
wherein the first transistor has a first electrode connected to the QP-node, and a second electrode connected to the gate-off voltage input terminal.
9 . The gate driver of claim 7 ,
wherein each of the plurality of stages further comprises a first capacitor connected between the QP-node and the second clock input terminal.
10 . The gate driver of claim 7 ,
wherein each of the plurality of stages further comprises a second capacitor connected between the QB-node and the gate-off voltage input terminal, and
wherein the QB-node is configured to be at a gate-off voltage during a first period and a second period.
11 . The gate driver of claim 7 , further comprising:
a sixth transistor having a gate electrode connected to the QB-node, a first electrode connected to the Q1-node, and a second electrode connected to the gate-off voltage input terminal.
12 . The gate driver of claim 7 , further comprising:
a seventh transistor having a gate electrode connected to a gate-on voltage input terminal, a first electrode connected to the pull-up transistor, and a second electrode connected to the fifth transistor.
13 . The gate driver of claim 7 ,
wherein the first transistor is turned on, such that a gate-off voltage is applied to the QP-node, the third transistor is turned on, such that the gate-off voltage is applied to the QB-node, and the fifth transistor is turned on, such that a gate-on voltage is applied to the Q1-node, while a start signal is a gate-on voltage.
14 . The gate driver of claim 7 ,
wherein the first transistor is turned on, such that a gate-off voltage is applied to the QP-node, and the third transistor is turned on, such that the gate-off voltage is applied to the QB-node, while an output signal of the gate driver is a gate-on voltage.
15 . The gate driver of claim 7 ,
wherein the first electrode of the fifth transistor is directly connected to the gate electrode of the first transistor and to the gate electrode of the third transistor.
16 . The gate driver of claim 1 , wherein the gate electrode of the first transistor is directly connected to the start signal input terminal.
17 . The gate driver of claim 7 , wherein the gate electrode of the third transistor is directly connected to the first electrode of the fifth transistor.