Shift register unit, shift register, display panel and display
The disclosure discloses a shift register unit, a shift register, a display panel and a display, and belongs to display driving technology. The shift register unit comprises: twelve transistors M 1 , M 2 , . . . , M 12 ; one capacitor C 1 ; four signal input terminals INPUT, RESET, CLK, CLKB; one signal output terminal OUTPUT; and one or more power supply terminals. The disclosure may decrease the output delay and attenuation, and improve an anti-interference capability, so that the shift register may operate stably and a driving margin of the shift register could be increased.
1. A shift register unit, comprising: twelve transistors M 1 , M 2 , M 3 , M 4 , M 5 , M 6 , M 7 , M 8 , M 9 , M 10 , M 11 , and, M 12 ; one capacitor C 1 ; four signal input terminals INPUT, RESET, CLK, CLKB; one signal output terminal OUTPUT; and one power supply terminal VSS, and connection relationships among them are as follows:
a gate of the M 1 is connected to both the signal input terminal INPUT and gates of the M 6 and M 9 , and a source of the M 1 is connected to drains of the M 2 and M 11 ;
a gate of the M 2 is connected to the signal input terminal RESET;
both a gate and a drain of the M 5 are connected to the signal input terminal CLKB, and a source of the M 5 is connected to drains of the M 6 and M 7 ;
a gate of the M 8 is connected to the source of the M 5 , a drain of the M 8 is connected to both drains of the M 9 and M 10 and gates of the M 11 and M 12 ;
a drain of the M 3 is connected to the signal input terminal CLK, a gate of the M 3 is connected to one end of the capacitor C 1 and the source of the M 1 , and a source of the M 3 is connected to the other end of the capacitor C 1 , gates of the M 7 and M 10 , drains of the M 12 and M 4 and the signal output terminal OUTPUT;
sources of M 2 , M 11 , M 6 , M 7 , M 9 , M 10 , M 12 and M 4 are connected to the power supply terminal VSS, and a gate of the M 4 is connected to the signal input terminal RESET;
said shift register unit further comprises two additional signal input terminals: fifth signal input terminal and sixth signal input terminal, a drain of the M 1 is connected to the fifth signal input terminal, and when the gate of the M 1 is at the high level, the signal input terminal at the drain of the M 1 is also at a high level; a source of the M 8 is connected to the sixth signal input terminal, and when the gate of the M 8 is at the high level, the signal input terminal at the source of the M 8 is also at a high level.
2. The shift register unit of claim 1 , wherein the shift register unit further comprises two power supply terminals VDD 1 and VDD 2 ; the fifth signal input terminal connected with the drain of the M 1 is connected to said power supply terminal VDD 1 ; and the sixth signal input terminal connected with the source of the M 8 is connected to the power supply terminal VDD 2 .
3. The shift register unit of claim 1 , wherein the fifth signal input terminal connected with the drain of the M 1 is connected to said signal input terminal INPUT, and the drain of the M 1 is further connected to gates of the M 6 and M 9 ; the sixth signal input terminal connected with the source of the M 8 is connected to the signal input terminal CLKB, and the source of the M 8 is further connected to both the gate and the drain of the M 5 .
4. The shift register unit of claim 1 , wherein the shift register unit further comprises one power supply terminal VDD 1 ; the fifth signal input terminal connected with the drain of the M 1 is connected to said power supply terminal VDD 1 ; the sixth signal input terminal connected with the source of the M 8 is connected to the signal input terminal CLKB, and the source of the M 8 is further connected to both the gate and the drain of the M 5 .
5. A shift register, comprising a plurality of shift register units, each shift register unit comprises: twelve transistors M 1 , M 2 , M 3 , M 4 , M 5 , M 6 , M 7 , M 8 , M 9 , M 10 , M 11 and, M 12 ; one capacitor C 1 ; four signal input terminals INPUT, RESET, CLK, CLKB; one signal output terminal OUTPUT; and one power supply terminal VSS, and connection relationships among them are as follows:
a gate of the M 1 is connected to both the signal input terminal INPUT and gates of the M 6 and M 9 , and a source of the M 1 is connected to drains of the M 2 and M 11 ;
a gate of the M 2 is connected to the signal input terminal RESET;
both a gate and a drain of the M 5 are connected to the signal input terminal CLKB, and a source of the M 5 is connected to drains of the M 6 and M 7 ;
a gate of the M 8 is connected to the source of the M 5 , a drain of the M 8 is connected to both drains of the M 9 and M 10 and gates of the M 11 and M 12 ; a drain of the M 3 is connected to the signal input terminal CLK, a gate of the M 3 is connected to one end of the capacitor C 1 and the source of the M 1 , and a source of the M 3 is connected to the other end of the capacitor C 1 , gates of the M 7 and M 10 , drains of the M 12 and M 4 and the signal output terminal OUTPUT;
sources of M 2 , M 11 , M 6 , M 7 , M 9 , M 10 , M 12 and M 4 are connected to the power supply terminal VSS, and a gate of the M 4 is connected to the signal input terminal RESET;
said shift register unit further comprises two additional signal input terminals: fifth signal input terminal and sixth signal input terminal, a drain of the M 1 is connected to the fifth signal input terminal, and when the gate of the M 1 is at the high level, the signal input terminal at the drain of the M 1 is also at a high level; a source of the M 8 is connected to the sixth signal input terminal, and when the gate of the M 8 is at the high level, the signal input terminal at the source of the M 8 is also at a high level.
6. The shift register of claim 5 , wherein the shift register unit further comprises two power supply terminals VDD 1 and VDD 2 ; the fifth signal input terminal connected with the drain of the M 1 is connected to said power supply terminal VDD 1 ; and the sixth signal input terminal connected with the source of the M 8 is connected to the power supply terminal VDD 2 .
7. The shift register of claim 5 , wherein the fifth signal input terminal connected with the drain of the M 1 is connected to said signal input terminal INPUT, and the drain of the M 1 is further connected to gates of the M 6 and M 9 ; the sixth signal input terminal connected with the source of the M 8 is connected to the signal input terminal CLKB, and the source of the M 8 is further connected to both the gate and the drain of the M 5 .
8. The shift register of claim 5 , wherein the shift register unit further comprises one power supply terminal VDD 1 ; the fifth signal input terminal connected with the drain of the M 1 is connected to said power supply terminal VDD 1 ; the sixth signal input terminal connected with the source of the M 8 is connected to the signal input terminal CLKB, and the source of the M 8 is further connected to both the gate and the drain of the M 5 .
9. The shift register of claim 5 , wherein the shift register comprises a cascade of said plurality of shift register units.
10. A display panel, comprising a shift register as a gate driver of the display panel, said shift register includes a plurality of shift register units, each shift register unit comprises: twelve transistors M 1 , M 2 , M 3 , M 4 , M 5 , M 6 , M 7 , M 8 , M 9 , M 10 , M 11 , and, M 12 ; one capacitor C 1 ; four signal input terminals INPUT, RESET, CLK, CLKB; one signal output terminal OUTPUT; and one power supply terminal VSS, and connection relationships among them are as follows:
a gate of the M 1 is connected to both the signal input terminal INPUT and gates of the M 6 and M 9 , and a source of the M 1 is connected to drains of the M 2 and M 11 ; a gate of the M 2 is connected to the signal input terminal RESET;
both a gate and a drain of the M 5 are connected to the signal input terminal CLKB, and a source of the M 5 is connected to drains of the M 6 and M 7 ;
a gate of the M 8 is connected to the source of the M 5 , a drain of the M 8 is connected to both drains of the M 9 and M 10 and gates of the M 11 and M 12 ;
a drain of the M 3 is connected to the signal input terminal CLK, a gate of the M 3 is connected to one end of the capacitor C 1 and the source of the M 1 , and a source of the M 3 is connected to the other end of the capacitor C 1 , gates of the M 7 and M 10 , drains of the M 12 and M 4 and the signal output terminal OUTPUT;
sources of M 2 , M 11 , M 6 , M 7 , M 9 , M 10 , M 12 and M 4 are connected to the power supply terminal VSS, and a gate of the M 4 is connected to the signal input terminal RESET;
said shift register unit further comprises two additional signal input terminals: fifth signal input terminal and sixth signal input terminal, a drain of the M 1 is connected to the fifth signal input terminal, and when the gate of the M 1 is at the high level, the signal input terminal at the drain of the M 1 is also at a high level; a source of the M 8 is connected to the sixth signal input terminal, and when the gate of the M 8 is at the high level, the signal input terminal at the source of the M 8 is also at a high level.
11. The display panel of claim 10 , wherein the shift register unit further comprises two power supply terminals VDD 1 and VDD 2 ; the fifth signal input terminal connected with the drain of the M 1 is connected to said power supply terminal VDD 1 ; and the sixth signal input terminal connected with the source of the M 8 is connected to the power supply terminal VDD 2 .
12. The display panel of claim 10 , wherein the fifth signal input terminal connected with the drain of the M 1 is connected to said signal input terminal INPUT, and the drain of the M 1 is further connected to gates of the M 6 and M 9 ; the sixth signal input terminal connected with the source of the M 8 is connected to the signal input terminal CLKB, and the source of the M 8 is further connected to both the gate and the drain of the M 5 .
13. The display panel of claim 10 , wherein the shift register unit further comprises one power supply terminal VDD 1 ; the fifth signal input terminal connected with the drain of the M 1 is connected to said power supply terminal VDD 1 ; the sixth signal input terminal connected with the source of the M 8 is connected to the signal input terminal CLKB, and the source of the M 8 is further connected to both the gate and the drain of the M 5 .
14. A display, comprising a display panel, the display panel comprises a shift register as a gate driver of the display panel, said shift register includes a plurality of shift register units, each shift register unit comprises: twelve transistors M 1 , M 2 , M 3 , M 4 , M 5 , M 6 , M 7 , M 8 , M 9 , M 10 , M 11 , and, M 12 ; one capacitor C 1 ; four signal input terminals INPUT, RESET, CLK, CLKB; one signal output terminal OUTPUT; and one power supply terminal VSS, and connection relationships among them are as follows:
a gate of the M 1 is connected to both the signal input terminal INPUT and gates of the M 6 and M 9 , and a source of the M 1 is connected to drains of the M 2 and M 11 ;
a gate of the M 2 is connected to the signal input terminal RESET;
both a gate and a drain of the M 5 are connected to the signal input terminal CLKB, and a source of the M 5 is connected to drains of the M 6 and M 7 ;
a gate of the M 8 is connected to the source of the M 5 , a drain of the M 8 is connected to both drains of the M 9 and M 10 and gates of the M 11 and M 12 ;
a drain of the M 3 is connected to the signal input terminal CLK, a gate of the M 3 is connected to one end of the capacitor C 1 and the source of the M 1 , and a source of the M 3 is connected to the other end of the capacitor C 1 , gates of the M 7 and M 10 , drains of the M 12 and M 4 and the signal output terminal OUTPUT;
sources of M 2 , M 11 , M 6 , M 7 , M 9 , M 10 , M 12 and M 4 are connected to the power supply terminal VSS, and a gate of the M 4 is connected to the signal input terminal RESET;
said shift register unit further comprises two additional signal input terminals: fifth signal input terminal and sixth signal input terminal, a drain of the M 1 is connected to the fifth signal input terminal, and when the gate of the M 1 is at the high level, the signal input terminal at the drain of the M 1 is also at a high level; a source of the M 8 is connected to the sixth signal input terminal, and when the gate of the M 8 is at the high level, the signal input terminal at the source of the M 8 is also at a high level.
15. The display of claim 14 , wherein the shift register unit further comprises two power supply terminals VDD 1 and VDD 2 ; the fifth signal input terminal connected with the drain of the M 1 is connected to said power supply terminal VDD 1 ; and the sixth signal input terminal connected with the source of the M 8 is connected to the power supply terminal VDD 2 .
16. The display of claim 14 , wherein the fifth signal input terminal connected with the drain of the M 1 is connected to said signal input terminal INPUT, and the drain of the M 1 is further connected to gates of the M 6 and M 9 ; the sixth signal input terminal connected with the source of the M 8 is connected to the signal input terminal CLKB, and the source of the M 8 is further connected to both the gate and the drain of the M 5 .
17. The display of claim 14 , wherein the shift register unit further comprises one power supply terminal VDD 1 ; the fifth signal input terminal connected with the drain of the M 1 is connected to said power supply terminal VDD 1 ; the sixth signal input terminal connected with the source of the M 8 is connected to the signal input terminal CLKB, and the source of the M 8 is further connected to both the gate and the drain of the M 5 .