IP Library Granted Patent US 11,037,907
Granted Patent B2
US 11,037,907 · App. 16/521,695 · Granted Jun 15, 2021

Semiconductor package and related methods

Inventors: Seungwon Im (Bucheon, KR); Oseob Jeon (Seoul, KR); JoonSeo Son (Seoul, KR); Mankyo Jong (Bucheon, KR); Olaf Zschieschang (Vaterstetten, DE)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01L25/0657H01L21/565H01L23/3735H01L23/5385H01L24/00H01L25/072H01L23/051H01L23/3107H01L24/29H01L24/32H01L24/33H01L2224/291H01L2224/32227H01L2224/32245H01L2224/33181H01L2224/83424H01L2224/83447H01L2225/06513H01L2225/06524H01L2225/06527H01L2225/06589
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Quick Facts
Patent No.
US 11,037,907
App. No.
16/521,695
Granted
Jun 15, 2021
Kind
B2
Abstract

Implementations of semiconductor packages may include: a first substrate having a first dielectric layer coupled between a first metal layer and a second metal layer; a second substrate having a second dielectric layer coupled between a third metal layer and a fourth metal layer. A first die may be coupled with a first electrical spacer coupled in a space between and coupled with the first substrate and the second substrate and a second die may be coupled with a second electrical spacer coupled in a space between and coupled with the first substrate and the second substrate.

Claims (37)

1. A semiconductor package comprising:

a first substrate;

a second substrate;

a first die coupled with a first electrical spacer coupled in a space between and coupled with the first substrate and the second substrate; and

a second die coupled with a second electrical spacer coupled in a space between and coupled with the first substrate and the second substrate;

wherein a width of the first substrate is wider than a corresponding width of the second substrate; and

wherein a length of the first substrate is shorter than a corresponding length of the second substrate.

2. The semiconductor package of claim 1 , wherein the width of the first substrate is configured to facilitate application of a mold compound to the first die and to the second die.

3. The semiconductor package of claim 1 , wherein:

the first substrate comprises a dielectric layer coupled between a first metal layer and a second metal layer.

4. The semiconductor package of claim 3 , wherein the first dielectric layer comprises an extension extending beyond a length of the first metal layer and a length of the second metal layer.

5. The semiconductor package of claim 1 , wherein the second substrate comprises a second dielectric layer coupled between a third metal layer and a fourth metal layer.

6. The semiconductor package of claim 5 , wherein the second dielectric layer comprises an extension extending beyond a length of the third metal layer and the fourth metal layer.

7. The semiconductor package of claim 1 , wherein the first substrate comprises a first metal layer and a second metal layer and the second substrate comprises a third metal layer and a fourth metal layer, wherein the first metal layer and the second metal layer are shorter than the third metal layer and the fourth metal layer.

8. The semiconductor package of claim 1 , wherein the first die and the second die are directly coupled to the first substrate.

9. The semiconductor package of claim 1 , wherein the first die is directly coupled to the first substrate and the second die is directly coupled to the second substrate.

10. The semiconductor package of claim 1 , wherein the substrates are biased relative to a molding apparatus by one of two or more springs.

11. The semiconductor package of claim 1 , wherein the first die and the second die comprise one of a bipolar junction transistor (BJT), an insulated gate bipolar transistor (IGBT), a superjunction field effect transistor (FET), a metal oxide semiconductor field effect transistor (MOSFET) device, a silicon carbide (SiC) device, a SiC BJT, a diode, a Schottky diode, or a combination thereof.

12. The semiconductor package of claim 1 , wherein the first electrical spacer is coupled with the first die through solder and the second electrical spacer is coupled with the second die through solder.

13. A power module comprising:

a first substrate;

a second substrate;

a first die coupled with a first electrical spacer coupled in a space between the first substrate and the second substrate;

a second die coupled with a second electrical spacer coupled in a space between the first substrate and the second substrate;

one or more flexible electrical supports directly coupled to the first substrate.

14. The power module of claim 13 , wherein the first die and the second die are directly coupled to the first substrate.

15. The power module of claim 13 , wherein the first die is directly coupled to the first substrate and the second die is directly coupled to the second substrate.

16. The power module of claim 13 , wherein the one or more flexible electrical supports comprise one of a spring, a pin, a flexible member, a sponge-like structure, a clip, or any combination thereof.

17. The power module of claim 13 , wherein the one or more flexible electrical supports comprise a shape comprising one of a square, a rectangle, a closed hexagonal, an open rhomboid, a closed rhomboid, a circle, an oval, an ellipse, or any combination thereof.

18. A power module comprising:

a first substrate comprising a first dielectric layer coupled between a first metal layer and a second metal layer;

a second substrate comprising a second dielectric layer coupled between a third metal layer and a fourth metal layer;

a first die coupled between the first substrate and the second substrate;

a second die coupled between the first substrate and the second substrate;

one or more flexible electrical supports directly coupled to the first substrate.

19. The power module of claim 18 , wherein the one or more flexible electrical supports comprise one of a spring, a pin, a flexible member, a sponge-like structure, a clip, or any combination thereof.

20. The power module of claim 18 , wherein one or more flexible electrical supports comprise a shape comprising one of a square, a rectangle, a closed hexagonal, an open rhomboid, a closed rhomboid, a circle, an oval, an ellipse, or any combination thereof.

Assignments (10)
SECURITY INTEREST Recorded Jul 13, 2023
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; GTAT CORPORATION
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064271/0971 →
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 058871, FRAME 0799 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 065653/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 051145, FRAME 0062 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064079/0474 →
SECURITY INTEREST Recorded Nov 12, 2021
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 058871/0799 →
RELEASE OF SECURITY INTEREST Recorded Oct 28, 2021
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 057969/0206 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 3, 2021
From: FAIRCHILD SEMICONDUCTOR CORPORATION
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 057694/0374 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 049857 FRAME: 0186. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 12, 2021
From: IM, SEUNGWON; JEON, OSEOB; SON, JOONSEO; JONG, MANKYO; ZSCHIESCHANG, OLAF
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 056224/0335 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EXCLUSION OF FAIRCHILD SEMICONDUCTOR CORPORATION OF CONVEYING PARTY PREVIOUSLY RECORDED ON REEL 051145 FRAME 0062. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Dec 3, 2019
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 051170/0781 →
SECURITY INTEREST Recorded Nov 26, 2019
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 051145/0062 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 25, 2019
From: IM, SEUNGWON; JEON, OSEOB; SON, JOONSEO; JONG, MANKYO; ZSCHIESCHANG, OLAF
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 049857/0185 →