IP Library Granted Patent US 11,264,492
Granted Patent B2
US 11,264,492 · App. 16/533,812 · Granted Mar 1, 2022

High electron mobility transistor and method for fabricating the same

Inventors: Shin-Chuan Huang (Tainan, TW); Chih-Tung Yeh (Taoyuan, TW); Chun-Ming Chang (Kaohsiung, TW); Bo-Rong Chen (Hsinchu County, TW); Wen-Jung Liao (Hsinchu, TW); Chun-Liang Hou (Hsinchu County, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L29/7786H01L21/26546H01L29/2003H01L29/205H01L29/66462
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Quick Facts
Patent No.
US 11,264,492
App. No.
16/533,812
Granted
Mar 1, 2022
Kind
B2
Abstract

A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; performing an implantation process through the hard mask to form a doped region in the barrier layer and the buffer layer; removing the hard mask and the barrier layer to form a first trench; forming a gate dielectric layer on the hard mask and into the first trench; forming a gate electrode on the gate dielectric layer; and forming a source electrode and a drain electrode adjacent to two sides of the gate electrode.

Claims (9)

1. A high electron mobility transistor (HEMT), comprising:

a buffer layer on a substrate;

a barrier layer on the buffer layer;

a gate electrode on the barrier layer;

a gate dielectric layer between the barrier layer and the gate electrode;

a doped region under the gate dielectric layer and overlapping the barrier layer and the buffer layer, wherein two sidewalls of the doped region are aligned with two sidewalls of the gate electrode;

a hard mask between the gate dielectric layer and the barrier layer, wherein a sidewall of the gate dielectric layer is aligned with a sidewall of the hard mask and a width of a bottom surface of the doped region is greater than a width of a bottom surface of the gate dielectric layer and equal to a width of a top surface the gate electrode; and

a source electrode and a drain electrode adjacent to two sides of the gate electrode on the buffer layer.

2. The HEMT of claim 1 , wherein the doped region comprises a U-shape.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 7, 2019
From: HUANG, SHIN-CHUAN; YEH, CHIH-TUNG; CHANG, CHUN-MING; CHEN, BO-RONG; LIAO, WEN-JUNG; HOU, CHUN-LIANG
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 049981/0819 →
Priority Claims (1)
TW 108124137 · Jul 9, 2019 · national
Continuity (1)
Related Publication 20210013334A1 · Jan 14, 2021
Cited By (15)
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