Successive approximation register analog-to-digital converter
An analog-to-digital converter includes a low voltage power supply rail, a high voltage power supply rail, successive approximation circuit, a level shifter, and a capacitive digital-to-analog converter (CDAC). The successive approximation circuitry is coupled to the low voltage power supply rail. The level shifter is coupled to the high voltage power supply rail and includes inputs coupled to first outputs of the successive approximation circuitry. The CDAC includes a first segment and a second segment. The first segment includes a first plurality of capacitors, and a first plurality of switches coupled to outputs of the level shifter. The second segment includes a second plurality of capacitors, and a second plurality of switches coupled to second outputs of the successive approximation circuitry.
1. An analog-to-digital converter, comprising:
a low voltage power supply terminal;
a high voltage power supply terminal;
successive approximation circuitry coupled to the low voltage power supply terminal;
a level shifter coupled to the high voltage power supply terminal and comprising inputs coupled to first outputs of the successive approximation circuitry;
a capacitive digital-to-analog converter (CDAC) comprising:
a first segment comprising:
a first plurality of capacitors; and
a first plurality of switches coupled to outputs of the level shifter; and
a second segment comprising:
a second plurality of capacitors; and
a second plurality of switches coupled to second outputs of the successive approximation circuitry.
2. The analog-to-digital converter of claim 1 , wherein:
the first plurality of switches is configured to operate at a voltage of the high voltage power supply; and
the second plurality of switches is configured to operate at a voltage of the low voltage power supply.
3. The analog-to-digital converter of claim 1 , further comprising:
a reference voltage terminal;
a buffer circuit coupled to the high voltage power supply terminal, and comprising an output coupled to the first plurality of switches and the reference voltage terminal.
4. The analog-to-digital converter of claim 3 , further comprising a voltage divider coupled to the output of the buffer circuit.
5. The analog-to-digital converter of claim 4 , wherein:
the buffer circuit is a first buffer circuit; and
the analog-to-digital converter comprises a second buffer circuit coupled to the low voltage power supply terminal, and comprising:
an input coupled to the voltage divider; and
an output coupled to the second plurality of switches.
6. The analog-to-digital converter of claim 4 , wherein the voltage divider is configured to divide output voltage of the buffer circuit by four.
7. The analog-to-digital converter of claim 1 , further comprising a signal input terminal, wherein all capacitors of the CDAC that are coupled to the signal input terminal are disposed in the first segment.
8. The analog-to-digital converter of claim 1 , further comprising a comparator coupled to the CDAC and the successive approximation circuitry.
9. The analog-to-digital converter of claim 1 , wherein the first segment is configured to convert bits of higher significance than the second segment.
10. An analog-to-digital converter, comprising:
a reference voltage terminal;
a first buffer circuit comprising an output coupled to the reference voltage terminal;
a voltage divider comprises an input coupled to the output of the first buffer circuit;
a second buffer circuit comprising an input coupled to an output of the voltage divider;
successive approximation circuitry;
a level shifter coupled to first outputs of the successive approximation circuitry;
a capacitive digital-to-analog converter (CDAC) comprising:
a first segment comprising:
a first plurality of capacitors; and
a first plurality of switches coupled to outputs of the level shifter, and the output of the first buffer circuit;
a second segment comprising:
a second plurality of capacitors; and
a second plurality of switches coupled to second outputs of the successive approximation circuitry, and an output of the second buffer circuit.
11. The analog-to-digital converter of claim 10 , wherein the voltage divider is configured to divide output voltage of the first buffer circuit by four.
12. The analog-to-digital converter of claim 10 , further comprising:
a low voltage power supply terminal;
a high voltage power supply terminal;
wherein:
the first buffer circuit and the level shifter are coupled to the high voltage power supply; and
the second buffer circuit and the successive approximation circuitry are coupled to the low voltage power supply.
13. The analog-to-digital converter of claim 10 , further comprising a signal input terminal; wherein all capacitors of the CDAC coupled to the signal input terminal are disposed in the first segment.
14. The analog-to-digital converter of claim 10 , wherein the first segment is configured to convert bits of higher significance than the second segment.