Granted Patent B2

US 12,199,626 · App. 17/973,785 · Granted Jan 14, 2025

Inventors: Hong Soon Nam (Daejeon, KR); Jae Young Kim (Seoul, KR); Youn Kwae Jeong (Daejeon, KR)

Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

H03M1/0617

Abstract

Claims (39)

1. A dynamic high-resolution analog to digital converter (ADC) comprising:

a sample and hold circuit configured to receive an analog signal from a sensor, sample the analog signal in units of time, and hold a size of the analog signal during a sampling period;

a dynamic amplifier connected to the sample and hold circuit and configured to amplify, by as much as a first gain, the sampled-and-held analog signal received from the sample and hold circuit;

a digital to analog converter (DAC) configured to convert a digital signal input from a decoder into an analog signal;

a residue signal amplifier connected at one input thereof to the dynamic amplifier and at another input thereof to the DAC and configured to calculate a difference between an output signal of the dynamic amplifier and an output signal of the DAC and amplify the difference by as much as a second gain;

an analog to digital converter (ADC) connected to the residue signal amplifier and configured to convert an output signal of the residue signal amplifier into a digital signal; and

the decoder connected to the ADC and configured to decode, into digital data, an output signal of the ADC input by the ADC,

wherein the decoder is connected to the dynamic amplifier and controls the first gain of the dynamic amplifier, and is connected to the residual signal amplifier and controls the second gain of the residue signal amplifier.

2. The dynamic high-resolution ADC of claim 1 , wherein the first gain is initialized to an initial value for every sampling period and is reduced by a factor of ½ from the initial value whenever clipping occurs since an input signal of the ADC exceeds a range of an input signal that the ADC is able to receive.

3. The dynamic high-resolution ADC of claim 1 , wherein the decoder controls the first gain to be reduced by a factor of ½ from the initial value of the first gain whenever clipping occurs since an input signal of the ADC exceeds a range of an input signal that the ADC is able to receive.

4. The dynamic high-resolution ADC of claim 1 , wherein the second gain:

has an initial value of 1 and is initialized to 1 for every sampling period; and

is determined to be an output of the ADC at the time of no occurrence of clipping, where the clipping does not occur since an input signal of the ADC is within a range of an input signal that the ADC is able to receive.

5. The dynamic high-resolution ADC of claim 1 , wherein the decoder is configured to control the second gain to be determined to be an output of the ADC at the time of no occurrence of clipping, where the clipping does not occur since an input signal of the ADC is within a range of an input signal that the ADC is able to receive.

6. The dynamic high-resolution ADC of claim 1 , wherein the DAC is configured to:

have an output initial value of 0 and be initialized to an initial value for every sampling period; and

receive the output signal of the ADC input by the decoder and convert the output signal of the ADC into an analog signal.

7. The dynamic high-resolution ADC of claim 1 , wherein the decoder is configured to:

control the first gain of the dynamic amplifier and the second gain of the residue signal amplifier; and

decode a digital signal into the digital data, based on the output signal of the ADC when the second gain is 1 and the output signal of the ADC when the second gain is not 1.

8. A method of converting analog to digital by a dynamic high-resolution analog to digital converter (ADC), the method comprising:

performing sampling and holding operation, in which a sample and hold circuit receiving an analog signal from a sensor samples the analog signal and holds a size of the analog signal during a sampling period;

performing a conversion operation of obtaining a first digital signal, in which a dynamic amplifier receiving the sampled-and-held analog signal from the sample and hold circuit amplifies a size of the sampled-and-held analog signal, and the sampled-and-held analog signal with the amplified size is converted into the first digital signal by a residue signal amplifier, which is configured to amplify a difference between two signals connected respectively through both inputs of the residue signal amplifier to and inputted by both of the dynamic amplifier and a digital to analog converter (DAC), and by an ADC, which is connected to the residue signal amplifier;

performing a conversion operation of obtaining a second digital signal, in which the ADC converts a signal not converted into the first digital signal among the sampled-and-held analog signal into a second digital signal; and

performing a decoding operation, in which a decoder connected to the ADC decodes the analog signal into digital data based on the first digital signal and the second digital signal, wherein the decoder is connected to the dynamic amplifier and controls a first gain of the dynamic amplifier, and is connected to the residual signal amplifier and controls a second gain of the residue signal amplifier.

9. The method of claim 8 , wherein the first digital signal is a signal, in which the sampled-and-held analog signal is controlled within a range of an input signal that the ADC is able to receive, and the controlled sampled-and-held analog signal is converted into a digital signal.

10. The method of claim 8 , wherein the performing of the conversion operation of obtaining the first digital signal comprises:

operation A determining whether an output signal of the ADC, to which the sampled-and-held analog signal is input, is a maximum output signal of the ADC, based on the first gain of the dynamic amplifier and the second gain of the residue signal amplifier;

operation B controlling the first gain to be ½ of the current first gain, where an output signal of the ADC, to which the sampled-and-held analog signal is input, is a maximum output signal of the ADC;

operation C determining whether a number of loops is less than a maximum number of extension bits; and

operation D, in which the ADC converts the sampled-and-held analog signal into the first digital signal, based on the controlled first gain, the maximum number of extension bits, and the second gain, where the number of loops is the maximum number of extension bits.

11. The method of claim 10 , further comprising operation E determining a number of extension bits to be the number of loops and controlling the second gain with the first digital signal, where the output signal of the ADC, to which the sampled-and-held analog signal is input, is less than the maximum output signal of the ADC.

12. The method of claim 10 , further comprising operation F increasing the number of loops by 1 and repeating operations A to D, where the number of loops is less than the maximum number of extension bits.

13. The method of claim 10 , wherein:

the first gain is initialized to an initial value for every sampling period, and

the second gain has an initial value of 1 and is initialized for every sampling period.

14. The method of claim 8 , wherein the performing of the conversion operation of obtaining the second digital signal comprises:

amplifying, by as much as the second gain, a difference between the sampled-and-held analog signal amplified by the dynamic amplifier and the first digital signal converted into an analog signal by the DAC; and

converting the amplified signal into a second digital signal by the ADC.

Assignments (1)

Priority Claims (2)

Continuity (1)

References Cited (24)

Cited By (1)

US 12,732,205