Memory device, driving method thereof, semiconductor device, electronic component, and electronic device
A memory device includes a memory cell, a replica cell, a read circuit, a write wordline, a read wordline, a dummy read wordline, a write bitline, a read bitline, a reference bitline, a sourceline, and a first wiring. The memory cell is electrically connected to the write wordline, the read wordline, the write bitline, the read bitline, and the sourceline. The read circuit outputs a potential based on the result of comparing the potential of the reference bitline and the potential of the read bitline. The replica cell includes a first transistor and a second transistor. The first transistor and the second transistor are electrically connected to each other in series between the bitline and the sourceline. A gate of the first transistor and a gate of the second transistor are electrically connected to a dummy read wordline and the first wiring, respectively.
1. A semiconductor device comprising:
a memory cell comprising:
a first transistor; and
a second transistor;
a third transistor;
a fourth transistor;
a write bit line;
a read bit line;
a source line;
a reference read bit line; and
a read circuit,
wherein one of a source and a drain of the first transistor is electrically connected to the write bit line,
wherein the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor,
wherein one of a source and a drain of the second transistor is electrically connected to the read bit line,
wherein the other of the source and the drain of the second transistor is electrically connected to the source line,
wherein one of a source and a drain of the third transistor is electrically connected to the reference read bit line,
wherein the other of the source and the drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,
wherein the other of the source and the drain of the fourth transistor is electrically connected to the source line,
wherein a first input terminal of the read circuit is directly connected to the read bit line,
wherein a second input terminal of the read circuit is electrically connected to the reference read bit line,
wherein a gate of the first transistor and a gate of the third transistor are electrically connected to a row circuit through a first word line and a second word line, respectively, and
wherein a gate of the fourth transistor is directly connected to a power supply line.
2. The semiconductor device according to claim 1 ,
wherein the read circuit is configured to compare a potential of the read bit line with a potential of the reference read bit line and output a potential based on the comparison result.
3. The semiconductor device according to claim 1 ,
wherein the first transistor comprises a channel formation region comprising an oxide semiconductor.
4. The semiconductor device according to claim 1 ,
wherein each of the second transistor, the third transistor and the fourth transistor is a p-channel transistor.
5. The semiconductor device according to claim 1 ,
wherein the second transistor, the third transistor, and the fourth transistor are the same in conductivity type.
6. A semiconductor device comprising:
a memory cell comprising:
a first transistor;
a second transistor; and
a capacitor;
a third transistor;
a fourth transistor;
a read word line;
a write bit line;
a read bit line;
a source line;
a reference read bit line; and
a read circuit,
wherein one of a source and a drain of the first transistor is electrically connected to the write bit line,
wherein the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor,
wherein a first electrode of the capacitor is electrically connected to the gate of the second transistor,
wherein a second electrode of the capacitor is electrically connected to the read word line,
wherein one of a source and a drain of the second transistor is electrically connected to the read bit line,
wherein the other of the source and the drain of the second transistor is electrically connected to the source line,
wherein one of a source and a drain of the third transistor is electrically connected to the reference read bit line,
wherein the other of the source and the drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,
wherein the other of the source and the drain of the fourth transistor is electrically connected to the source line,
wherein a first input terminal of the read circuit is directly connected to the read bit line,
wherein a second input terminal of the read circuit is electrically connected to the reference read bit line,
wherein a gate of the first transistor and a gate of the third transistor are electrically connected to a row circuit through a first word line and a second word line, respectively, and
wherein a gate of the fourth transistor is directly connected to a power supply line.
7. The semiconductor device according to claim 6 ,
wherein the read circuit is configured to compare a potential of the read bit line with a potential of the reference read bit line and output a potential based on the comparison result.
8. The semiconductor device according to claim 6 ,
wherein the first transistor comprises a channel formation region comprising an oxide semiconductor.
9. The semiconductor device according to claim 6 ,
wherein each of the second transistor, the third transistor and the fourth transistor is a p-channel transistor.
10. The semiconductor device according to claim 6 ,
wherein the second transistor, the third transistor, and the fourth transistor are the same in conductivity type.