Granted Patent B2

US 12,380,938 · App. 18/409,150 · Granted Aug 5, 2025

Inventors: Yuto Yakubo (Kanagawa, JP); Takahiko Ishizu (Kanagawa, JP)

Assignee: Semiconductor Energy Laboratory Co., Ltd.

G11C11/405G11C11/4096H10B12/00H10D30/6734H10D30/6755H10D86/423H10D86/441H10D86/481H10D86/60

Abstract

Claims (51)

1. A memory device comprising:

a memory cell array comprising a first memory cell and a second memory cell;

a reading circuit electrically connected to the memory cell array; and

a processor electrically connected to the memory cell array and the reading circuit,

wherein each of the reading circuit and the processor comprises a transistor comprising silicon in a channel formation region,

wherein each of the first memory cell and the second memory cell comprise a transistor comprising a metal oxide in a channel formation region,

wherein the first memory cell is electrically connected to the reading circuit through a first wiring,

wherein the second memory cell is electrically connected to the reading circuit through a second wiring,

wherein the first wiring is configured to flow a first current corresponding to first data retained in the first memory cell from the reading circuit to the first memory cell,

wherein the second wiring is configured to flow a second current corresponding to second data retained in the second memory cell from the reading circuit to the second memory cell, and

wherein the reading circuit is configured to compare the first current and the second current and output a voltage corresponding to data read from the first memory cell.

2. The memory device according to claim 1 , wherein the memory cell array is provided over the processor and the reading circuit.

3. The memory device according to claim 1 , wherein the second memory cell is a reference memory cell of the first memory cell.

4. The memory device according to claim 1 ,

wherein the reading circuit comprises a first transistor and a second transistor,

wherein the first transistor and the second transistor are n-channel transistors,

wherein a first terminal of the first transistor is electrically connected to the first wiring, and

wherein a first terminal of the second transistor is electrically connected to the second wiring.

5. The memory device according to claim 4 ,

wherein the reading circuit further comprises a third transistor and a fourth transistor,

wherein the third transistor and the fourth transistor are p-channel transistors,

wherein a second terminal of the first transistor is electrically connected to a first terminal of the third transistor, and

wherein a second terminal of the second transistor is electrically connected to a first terminal of the fourth transistor.

6. The memory device according to claim 5 , wherein each of the first transistor, the second transistor, the third transistor, and the fourth transistor comprises silicon in a channel formation region.

7. The memory device according to claim 5 ,

wherein each of the first transistor and the second transistor comprises the metal oxide in a channel formation region, and

wherein each of the third transistor and the fourth transistor comprises silicon in a channel formation region.

8. An electronic device comprising the memory device according to claim 1 and a housing.

9. A memory device comprising:

a memory cell array comprising a first memory cell and a second memory cell;

a reading circuit electrically connected to the memory cell array; and

a processor electrically connected to the memory cell array and the reading circuit,

wherein each of the first memory cell and the second memory cell comprises a transistor comprising a metal oxide in a channel formation region,

wherein the metal oxide comprises at least indium,

wherein the reading circuit comprises a first transistor and a second transistor each comprising silicon in a channel formation region,

wherein the first transistor and the second transistor are p-channel transistors,

wherein the first memory cell is electrically connected to the first transistor of the reading circuit through a first wiring,

wherein the second memory cell is electrically connected to the second transistor of the reading circuit through a second wiring,

wherein the first wiring is configured to flow a first current corresponding to first data retained in the first memory cell from the reading circuit to the first memory cell,

wherein the second wiring is configured to flow a second current corresponding to second data retained in the second memory cell from the reading circuit to the second memory cell, and

wherein the reading circuit is configured to compare the first current and the second current and output a voltage corresponding to data read from the first memory cell.

10. The memory device according to claim 9 , wherein the memory cell array is provided over the processor and the reading circuit.

11. The memory device according to claim 9 , wherein the second memory cell is a reference memory cell of the first memory cell.

12. The memory device according to claim 9 ,

wherein the reading circuit further comprises a third transistor and a fourth transistor,

wherein the third transistor and the fourth transistor are n-channel transistors,

wherein the first transistor is electrically connected to the first wiring through the third transistor, and

wherein the second transistor is electrically connected to the second wiring through the fourth transistor.

13. The memory device according to claim 12 , wherein each of the third transistor and the fourth transistor comprises silicon in a channel formation region.

14. The memory device according to claim 12 , wherein each of the third transistor and the fourth transistor comprises the metal oxide in a channel formation region.

15. An electronic device comprising the memory device according to claim 9 , and a housing.

Priority Claims (1)

Continuity (2)

References Cited (50)