Memory device
According to one embodiment, a memory device includes a memory cell; and a first circuit configured to perform first read for the memory cell and generate a first voltage, write first data to the memory cell that has undergone the first read, perform second read for the memory cell to which the first data written and generate a second voltage, generate a first current based on the first voltage, generate a second current based on the second voltage, and add a third current to one of the first current and the second current, thereby determining data stored in the memory cell at the time of the first read.
1. A memory device comprising:
a memory cell; and
a first circuit configured to perform first read for the memory cell and generate a first voltage,
write first data to the memory cell that has undergone the first read,
perform second read for the memory cell to which the first data is written and generate a second voltage,
generate a first current based on the first voltage,
generate a second current based on the second voltage, and
add a third current to one of the first current and the second current, thereby determining data stored in the memory cell at the time of the first read.
2. The device of claim 1 , wherein the first circuit comprises:
a preamplifier configured to generate the first voltage and the second voltage; and
a sense amplifier configured to generate the first current, the second current, and the third current and determine the data stored in the memory cell at the time of the first read.
3. The device of claim 2 , wherein
when performing the first read for the memory cell,
the preamplifier supplies a fourth current to the memory cell via a first path, and
supplies a fifth current that is a copy current of the fourth current to a first voltage generation unit via a second path electrically separated from the first path, and
when performing the second read for the memory cell,
the preamplifier supplies a sixth current to the memory cell via the first path, and
supplies a seventh current that is a copy current of the sixth current to a second voltage generation unit via the second path.
4. The device of claim 3 , wherein
when performing the first read for the memory cell,
the preamplifier supplies the fourth current to the memory cell via the first path using a first diode-connected transistor, and
when performing the second read for the memory cell,
the preamplifier supplies the sixth current to the memory cell via the first path using the first diode-connected transistor.
5. A method of controlling a memory device, comprising:
performing first read for a memory cell and generating a first voltage;
writing first data to the memory cell that has undergone the first read;
performing second read for the memory cell to which the first data is written and generating a second voltage;
generating a first current based on the first voltage;
generating a second current based on the second voltage; and
adding a third current to one of the first current and the second current, thereby determining data stored in the memory cell at the time of the first read.
6. A memory device comprising:
a memory cell; and
a first circuit configured to perform first read for the memory cell and generate a first voltage,
write first data to the memory cell that has undergone the first read,
perform second read for the memory cell to which the first data is written and generate a second voltage,
generate one of a third voltage based on the first voltage and a fourth voltage based on the second voltage using a shift circuit after generation of the second voltage,
generate a first current based on one of the first voltage and the third voltage,
generate a second current based on one of the second voltage and the fourth voltage, and
compare a magnitude of one of the first current and the second current, thereby determining data stored in the memory cell at the time of the first read.
7. The device of claim 6 , wherein the first circuit comprises:
a preamplifier configured to generate the first voltage, the second voltage, the third voltage, and the fourth voltage; and
a sense amplifier configured to generate the first current and the second current and determine the data stored in the memory cell at the time of the first read.
8. The device of claim 7 , wherein
when performing the first read for the memory cell,
the preamplifier charges the shift circuit to a fifth voltage, and after the generation of the second voltage, shares the fifth voltage as the second voltage from the shift circuit, thereby generating the fourth voltage.
9. The device of claim 8 , wherein the preamplifier comprises the shift circuit, and
the shift circuit comprises:
a first storage area configured to store the fifth voltage;
a first switch configured to store the fifth voltage in the first storage area; and
a second switch configured to share the fifth voltage as the second voltage.
10. The device of claim 8 , wherein the preamplifier comprises the shift circuit, and
the shift circuit comprises:
a second storage area configured to store the fifth voltage;
a third switch configured to store the fifth voltage in the second storage area; and
a fourth switch configured to discharge the second storage area.
11. The device of claim 7 , wherein
when performing the first read for the memory cell,
the preamplifier charges the shift circuit to a fifth voltage,
generates the first voltage based on a result of the first read and the fifth voltage, and
after the generation of the second voltage, discharges the shift circuit, thereby generating the third voltage based on the first voltage.
12. The device of claim 7 , wherein
when performing the first read for the memory cell,
the preamplifier supplies a third current to the memory cell via a first path, and
supplies a fourth current that is a copy current of the third current to a first voltage generation unit via a second path electrically separated from the first path, and
when performing the second read for the memory cell,
the preamplifier supplies a fifth current to the memory cell via the first path, and
supplies a sixth current that is a copy current of the fifth current to a second voltage generation unit via the second path.
13. The device of claim 12 , wherein
when performing the first read for the memory cell,
the preamplifier supplies the third current to the memory cell via the first path using a first diode-connected transistor, and
when performing the second read for the memory cell,
the preamplifier supplies the fifth current to the memory cell via the first path using the first diode-connected transistor.
14. The device of claim 12 , wherein
when performing the first read for the memory cell,
the preamplifier charges the shift circuit to a fifth voltage, and after the generation of the second voltage, shares the fifth voltage as the first voltage from the shift circuit, thereby generating the third voltage.
15. The device of claim 14 , wherein the preamplifier comprises the shift circuit, and
the shift circuit comprises:
a third storage area configured to store the fifth voltage;
a fifth switch configured to store the fifth voltage in the third storage area; and
a sixth switch configured to share the fifth voltage as the first voltage.
16. The device of claim 12 , wherein
when performing the first read for the memory cell,
the preamplifier charges the shift circuit to a fifth voltage,
generates the second voltage based on a result of the second read and the fifth voltage, and
after the generation of the second voltage, discharges the shift circuit, thereby generating the fourth voltage based on the second voltage.
17. The device of claim 16 , wherein the preamplifier comprises the shift circuit, and
the shift circuit comprises:
a fourth storage area configured to store the fifth voltage;
a seventh switch configured to store the fifth voltage in the fourth storage area; and
an eighth switch configured to discharge the fourth storage area.