Three-dimensional semiconductor memory device and a method of fabricating the same
A method of forming a semiconductor memory device includes stacking a plurality of alternating first insulating layers and first sacrificial layers on a substrate to form a first multilayer structure, forming a first hole through the first multilayer structure, forming a first semiconductor pattern in the first hole, stacking a plurality of alternating second insulating layers and second sacrificial layers on the first multilayer structure to form a second multilayer structure, forming a second hole through the second multilayer structure to be aligned with the first hole, forming a second semiconductor pattern in the second hole, forming a trench to expose sidewalls of the first and second insulating layers at a side of the first and second semiconductor patterns, removing at least some portions of the first and second sacrificial layers to form a plurality of recess regions, forming an information storage layer along surfaces of the plurality of recess regions, and forming a conductive pattern within each recess region.
1. A method of forming a semiconductor memory device, comprising:
stacking a plurality of alternating first insulating layers and first sacrificial layers on a substrate to form a first multilayer structure;
forming a first hole through the first multilayer structure;
forming a first semiconductor pattern in the first hole;
stacking a plurality of alternating second insulating layers and second sacrificial layers on the first multilayer structure to form a second multilayer structure;
forming a second hole through the second multilayer structure to be aligned with the first hole;
forming a second semiconductor pattern in the second hole;
forming a trench to expose sidewalls of the first and second insulating layers at a side of the first and second semiconductor patterns;
removing at least some portions of the first and second sacrificial layers to form a plurality of recess regions;
forming an information storage layer along surfaces of the plurality of recess regions; and
forming a conductive pattern within each recess region.
2. The method of claim 1 , wherein the first semiconductor pattern occupies the first hole, and the second semiconductor pattern occupies the second hole.
3. The method of claim 1 , wherein the first semiconductor pattern is disposed on a surface of the first hole, and the second semiconductor pattern is disposed on a surface of the second hole.
4. The method of claim 3 , further comprising forming a connection pad between the first semiconductor pattern and the second semiconductor pattern.
5. The method of claim 1 , wherein the information storage layer is formed in a single deposition process.
6. The method of claim 5 , wherein the single deposition process comprises chemical vapor deposition (CVD) or atomic layer deposition (ALD).
7. The method of claim 1 , wherein a thickness of the information storage layer is less than about half of a thickness of a recess region.
8. The method of claim 1 , wherein the information storage layer comprises an oxide-nitride-oxide (ONO) layer.
9. The method of claim 1 , wherein the information storage layer comprises a trap insulating layer, a floating gate electrode, conductive nano dots, a tunnel insulating layer or a blocking insulating layer.
10. The method of claim 1 , wherein the first and second sacrificial layers are removed substantially at a same time.
11. The method of claim 1 , wherein each recess region extends horizontally from the trench to the first and second semiconductor patterns.
12. The method of claim 1 , further comprising filling the trench with an insulating material.
13. The method of claim 1 , wherein removing the first and second sacrificial layers comprises isotropically etching the first and second sacrificial layers.
14. The method of claim 1 , further comprising removing a residual conductive pattern disposed outside each recess region.
15. A method of forming a semiconductor memory device, comprising:
stacking a plurality of alternating first insulating layers and first sacrificial layers on a substrate to form a first multilayer structure;
forming a first hole and a first trench through the first multilayer structure;
filling the first hole and the first trench with a sacrificial pattern;
stacking a plurality of alternating second insulating layers and second sacrificial layers on the first multilayer structure to form a second multilayer structure;
forming, through the second multilayer structure, a second hole exposing a top surface of the sacrificial pattern in the first hole;
removing the sacrificial pattern in the first hole;
forming a semiconductor pattern in the first and second holes;
forming, through the second multilayer structure, a second trench exposing a top surface of the sacrificial pattern in the first trench;
removing the sacrificial pattern in the first trench;
removing at least some portions of the first and second sacrificial layers to form a plurality of recess regions;
forming an information storage layer along surfaces of the plurality of recess regions; and
forming a conductive pattern within each recess region.
16. The method of claim 15 , wherein the semiconductor pattern is formed by a CVD process or an epitaxial growth process.
17. The method of claim 15 , wherein the semiconductor pattern is formed to cover exposed sidewalls of the first and second holes.
18. The method of claim 17 , wherein the semiconductor pattern comprises a cup shaped lower pattern and a pipe shaped upper pattern.
19. The method of claim 15 , wherein the first and second holes comprise a plug type hole and the first and second trenches comprise a line type trench.
20. The method of claim 15 , wherein a thickness of the information storage layer is less than about half of a thickness of a recess region.
21. The method of claim 15 , wherein the information storage layer comprises an oxide-nitride-oxide (ONO) layer.
22. The method of claim 15 , wherein the information storage layer comprises a trap insulating layer, a floating gate electrode, conductive nano dots, a tunnel insulating layer or a blocking insulating layer.
23. The method of claim 15 , wherein the first and second sacrificial layers are removed substantially at a same time.
24. The method of claim 15 , wherein each recess region extends horizontally from the first and second trenches to the semiconductor pattern.
25. The method of claim 15 , wherein removing the first and second sacrificial layers comprises isotropically etching the first and second sacrificial layers.
26. The method of claim 15 , further comprising removing a residual conductive pattern disposed outside each recess region.
27. The method of claim 15 , further comprising filling the first and second trenches with an insulating material.