Package and manufacturing method thereof

1. A package, comprising:

a first die having a first bonding structure, wherein the first bonding structure comprises a first dielectric layer and first connectors embedded in the first dielectric layer;

a second die having a semiconductor substrate and a second bonding structure over the semiconductor substrate, wherein the second bonding structure comprises a second dielectric layer and second connectors embedded in the second dielectric layer, sidewalls of the second dielectric layer are aligned with sidewalls of the semiconductor substrate, the first dielectric layer is bonded to the second dielectric layer, the first connectors are bonded to the second connectors, a shape of the first connectors is substantially identical to a shape of the second connectors, and an active surface of the first die faces an active surface of the second die;

an encapsulant laterally encapsulating the second die; and

through insulating vias (TIV) penetrating through the encapsulant, wherein the TIVs are connected to the first bonding structure.

2. The package according to claim 1 , wherein the first dielectric layer is attached to the encapsulant and the second dielectric layer is laterally covered by the encapsulant.

3. The package according to claim 1 , wherein each first connector of the first connectors has a via portion and a trench portion stacked on the via portion, each second connector of the second connectors has a via portion and a trench portion stacked on the via portion, and the trench portion of the second connector is bonded to the trench portion of the first connector.

4. The package according to claim 1 , wherein the first bonding structure further comprises auxiliary connectors embedded in the first dielectric layer, and the auxiliary connectors are attached to the TIVs.

5. The package structure according to claim 1 , wherein the second die further comprises through semiconductor vias (TSV) penetrating through at least a portion of the second die.

6. The package structure according to claim 5 , further comprising:

under-ball metallurgy (UBM) patterns disposed on the encapsulant, wherein the UBM patterns are connected to the TIVs and the TSVs; and

conductive terminals disposed on the UBM patterns.

7. The package structure according to claim 6 , wherein at least one of the TSVs and at least one of the TIVs are connected to a same UBM pattern.

8. The package structure according to claim 6 , wherein multiple TSVs are connected to a same UBM pattern.

9. A package, comprising:

a first die, comprising:

a first semiconductor substrate;

first pads over the first semiconductor substrate;

first connectors on the first pads; and

a first dielectric layer encapsulating the first pads and the first connectors;

a second die having an active surface facing an active surface of the first die, comprising:

a second semiconductor substrate;

second pads over the second semiconductor substrate;

second connectors on the second pads, wherein the second connectors are directly in contact with the first connectors, and a shape of the first connectors is substantially identical to a shape of the second connectors; and

a second dielectric layer encapsulating the second pads and the second connectors, wherein the second dielectric layer is directly in contact with the first dielectric layer, and sidewalls of the second dielectric layer are aligned with sidewalls of the second semiconductor substrate; and

an encapsulant laterally encapsulating the second die, wherein the encapsulant is directly in contact with the first dielectric layer.

10. The package according to claim 9 , wherein the first die further comprises:

a first interconnection structure sandwiched between the first pads and the first semiconductor substrate; and

auxiliary connectors embedded in the first dielectric layer, wherein the auxiliary connectors are electrically connected to the first interconnection structure.

11. The package according to claim 10 , further comprising through insulating vias (TIV) penetrating through the encapsulant, wherein the TIVs are directly in contact with the auxiliary connectors.

12. The package according to claim 11 , wherein multiple auxiliary connectors are directly in contact with a same TIV.

13. The package according to claim 11 , wherein the second die further comprises:

a second interconnection structure sandwiched between the second pads and the second semiconductor substrate; and

through semiconductor vias (TSV) penetrating through the second semiconductor substrate.

14. The package structure according to claim 13 , wherein each TSV is partially wrapped around by the encapsulant.

15. The package structure according to claim 13 , further comprising:

under-ball metallurgy (UBM) patterns disposed on the encapsulant, wherein the UBM patterns are connected to the TIVs and the TSVs; and

conductive terminals disposed on the UBM patterns.

16. The package structure according to claim 15 , wherein multiple TSVs are connected to a same UBM pattern.

17. A manufacturing method of a package, comprising:

providing a semiconductor wafer having a first bonding structure formed thereon, wherein the first bonding structure comprises a first dielectric layer and first connectors embedded in the first dielectric layer;

bonding semiconductor dies to the semiconductor wafer through a hybrid bonding process, wherein each semiconductor die of the semiconductor dies has a semiconductor substrate, a second bonding structure formed on the semiconductor substrate, and through semiconductor vias (TSV) formed in the semiconductor substrate, the second bonding structure comprises a second dielectric layer and second connectors embedded in the second dielectric layer, the first dielectric layer and the first connectors of the first bonding structure are respectively hybrid bonded to the second dielectric layer and the second connectors of the second bonding structure, a shape of the first connectors is substantially identical to a shape of the second connectors, an active surface of the semiconductor wafer faces active surfaces of the semiconductor dies, and sidewalls of the second dielectric layer are aligned with sidewalls of the semiconductor substrate;

forming through insulating vias (TIV) to surround the semiconductor dies and to connect to the first bonding structure;

encapsulating semiconductor dies and the TIVs by a first encapsulant such that the TIVs penetrate through the first encapsulant;

removing a portion of each semiconductor die to form recesses;

filling a second encapsulant into the recesses; and

forming under-ball metallurgy (UBM) patterns and conductive terminals on the first encapsulant and the second encapsulant, wherein the UBM patterns are connected to the TIVs and the TSVs.

18. The method according to claim 17 , wherein a temperature of the hybrid bonding process ranges from about 150° C. to about 400° C.

19. The method according to claim 17 , wherein the portion of each semiconductor die is removed such that at least a portion of each TSV is protruded from the semiconductor dies.

20. The method according to claim 17 , wherein the encapsulating the semiconductor dies and the TIVs comprises:

forming a first encapsulant material over the semiconductor wafer to encapsulate the semiconductor dies and the TIVs; and

thinning the first encapsulant material and the semiconductor die until the TIVs and the TSVs are exposed.