CMOS anti-fuse cell
A CMOS anti-fuse cell is disclosed. In one aspect, an apparatus includes an N− well and an anti-fuse cell formed on the N− well. The anti-fuse cell includes a drain P+ diffusion deposited in the N− well, a source P+ diffusion deposited in the N− well, and an oxide layer deposited on the N− well and having an overlapping region that overlaps the drain P+ diffusion. A control gate is deposited on the oxide layer. A data bit of the anti-fuse cell is programmed when a voltage difference between the control gate and the drain P+ diffusion exceeds a voltage threshold of the oxide layer and forms a leakage path from the control gate to the drain P+ diffusion. The leakage path is confined to occur in the overlapping region.
1. A multi-time programmable (MTP) anti-fuse apparatus, comprising:
an N− well;
a select gate (SG) transistor formed on the N− well and having a SG P+ drain diffusion coupled to a bit line and a SG P+ source diffusion;
a plurality of one-time programmable (OTP) anti-fuse cells formed in series on the N− well, wherein each OTP anti-fuse cell includes an oxide layer deposited on the N− well, a control gate deposited on the oxide layer, a drain P+ diffusion deposited in the N− well and forming an overlapping region with the oxide layer, and a source P+ diffusion deposited in the N− well;
wherein the drain P+ diffusion of a first OTP anti-fuse cell is coupled to the SG P+ source diffusion, and the source P+ diffusions of each remaining OTP anti-fuse cell are coupled to the drain P+ diffusions of adjacent OTP anti-fuse cells;
wherein a selected OTP anti-fuse cell is programmed by enabling the select gate transistor and all OTP anti-fuse cells between the select gate transistor and the selected OTP anti-fuse cell, and applying programming conditions to the selected OTP anti-fuse cell; and
wherein the MTP anti-fuse apparatus is reprogrammed when a second selected OTP anti-fuse cell that is located between the select gate transistor and the selected OTP anti-fuse cell is programmed by enabling the select gate transistor and all OTP anti-fuse cells between the select gate transistor and the second selected OTP anti-fuse cell, and applying programming conditions to the second selected OTP anti-fuse cell.
2. The apparatus of claim 1 , wherein each OTP anti-fuse cell forms a PMOS transistor, and wherein the second selected OTP anti-fuse cell is read by enabling the select gate transistor and all OTP anti-fuse cells between the select gate transistor and the second selected OTP anti-fuse cell, and apply reading conditions to the second selected OTP anti-fuse cell.
3. The apparatus of claim 1 , wherein each OTP anti-fuse cell is programmed when a voltage difference between the control gate and the drain P+ diffusion exceeds a voltage threshold of the oxide layer and forms a leakage path through the oxide layer that is confined to occur in the overlapping region.
4. The apparatus of claim 3 , wherein the voltage threshold of the oxide layer is approximately 4 volts.
5. The apparatus of claim 1 , wherein the selected OTP anti-fuse cell is at least one OTP anti-fuse cell away from the select gate transistor, and wherein the second selected OTP anti-fuse cell can be any OTP anti-fuse cell located between the select gate transistor and the selected OTP anti-fuse cell.
6. The apparatus of claim 1 , wherein the selected OTP anti-fuse cell is programmed by:
applying 0 volts to the bit line, a gate terminal of the select gate transistor, and the control gates of all OTP anti-fuse cells between the select gate transistor and the selected OTP anti-fuse cell; and
applying 5 volts to the control gate of the selected OTP anti-fuse cell.
7. The apparatus of claim 6 , wherein the MTP anti-fuse apparatus is reprogrammed by:
applying 0 volts to the bit line, the gate terminal of the select gate transistor, and the control gates of all OTP anti-fuse cells between the select gate transistor and the second selected OTP anti-fuse cell; and
applying 5 volts to the control gate of the second selected OTP anti-fuse cell.
8. The apparatus of claim 1 , further comprising a second select gate transistor formed on the N− well and coupled to a last OTP anti-fuse cell and the bit line.
9. A method of operating a multi-time programmable (MTP) anti-fuse apparatus having an N− well, a select gate (SG) transistor formed on the N− well, the SG transistor having a SG P+ drain diffusion coupled to a bit line and a SG P+ source diffusion, the apparatus also having a plurality of one-time programmable (OTP) anti-fuse cells formed in series on the N− well, wherein each OTP anti-fuse cell includes an oxide layer deposited on the N− well, a control gate deposited on the oxide layer, a drain P+ diffusion deposited in the N− well and forming an overlapping region with the oxide layer, and a source P+ diffusion deposited in the N− well, and wherein the drain P+ diffusion of a first OTP anti-fuse cell is coupled to the SG P+ source diffusion, and the source P+ diffusions of each remaining OTP anti-fuse cell are coupled to the drain P+ diffusions of adjacent OTP anti-fuse cells, the method comprising:
applying a first voltage to the bit line;
applying a second voltage to a gate terminal of the control gate;
applying a third voltage to the control gates of all OTP anti-fuse cells between the select gate transistor and a selected OTP anti-fuse cell; and
applying a fourth voltage to the control gate of the selected OTP anti-fuse cell.
10. The method of claim 9 , wherein the first, second, and third voltages are 0 volts, and the fourth voltage is five volts.
11. The method of claim 9 , wherein the MTP anti-fuse apparatus is reprogrammed by performing operations of:
applying the first voltage to the bit line;
applying the second voltage to the gate terminal of the control gate;
applying the third voltage to the control gates of all OTP anti-fuse cells between the select gate transistor and a second selected OTP anti-fuse cell; and
applying the fourth voltage to the control gate of the second selected OTP anti-fuse cell.
12. The method of claim 11 , wherein the first, second, and third voltages are 0 volts, and the fourth voltage is five volts.
13. A multi-time programmable (MTP) anti-fuse apparatus, comprising:
a P− well;
a select gate (SG) transistor formed on the P− well and having a SG N+ drain diffusion coupled to a bit line and a SG N+ source diffusion;
a plurality of one-time programmable (OTP) anti-fuse cells formed in series on the P− well, wherein each OTP anti-fuse cell includes an oxide layer deposited on the P− well, a control gate deposited on the oxide layer, a drain N+ diffusion deposited in the P− well and forming an overlapping region with the oxide layer, and a source N+ diffusion deposited in the P− well;
wherein the drain N+ diffusion of a first OTP anti-fuse cell is coupled to the SG N+ source diffusion, and the source N+ diffusions of each remaining OTP anti-fuse cell are coupled to the drain N+ diffusions of adjacent OTP anti-fuse cells;
wherein a selected OTP anti-fuse cell is programmed by enabling the select gate transistor and all OTP anti-fuse cells between the select gate transistor and the selected OTP anti-fuse cell, and applying programming conditions to the selected OTP anti-fuse cell; and
wherein the MTP anti-fuse apparatus is reprogrammed when a second selected OTP anti-fuse cell that is located between the select gate transistor and the selected OTP anti-fuse cell is programmed by enabling the select gate transistor and all OTP anti-fuse cells between the select gate transistor and the second selected OTP anti-fuse cell, and applying programming conditions to the second selected OTP anti-fuse cell.
14. The apparatus of claim 13 , wherein each OTP anti-fuse cell forms an NMOS transistor, and wherein the second selected OTP anti-fuse cell is read by enabling the select gate transistor and all OTP anti-fuse cells between the select gate transistor and the second selected OTP anti-fuse cell, and apply reading conditions to the second selected OTP anti-fuse cell.
15. The apparatus of claim 13 , wherein each OTP anti-fuse cell is programmed when a voltage difference between the control gate and the drain N+ diffusion exceeds a voltage threshold of the oxide layer and forms a leakage path through the oxide layer that is confined to occur in the overlapping region.
16. The apparatus of claim 15 , wherein the voltage threshold of the oxide layer is approximately 4 volts.
17. The apparatus of claim 13 , wherein the selected OTP anti-fuse cell is at least one OTP anti-fuse cell away from the select gate transistor, and wherein the second selected OTP anti-fuse cell can be any OTP anti-fuse cell located between the select gate transistor and the selected OTP anti-fuse cell.
18. The apparatus of claim 13 , wherein the selected OTP anti-fuse cell is programmed by applying 5 volts to the bit line, a gate terminal of the select gate transistor, and the control gates of all OTP anti-fuse cells between the select gate transistor and the selected OTP anti-fuse cell, and applying 0 volts the control gate of the selected OTP anti-fuse cell.
19. The apparatus of claim 13 , wherein the MTP anti-fuse apparatus is reprogrammed by applying 5 volts to the bit line, the gate terminal of the select gate transistor, and the control gates of all OTP anti-fuse cells between the select gate transistor and the selected OTP anti-fuse cell, and applying 0 volts to the control gate of the second selected OTP anti-fuse cell.
20. The apparatus of claim 13 , further comprising a second select gate transistor formed on the P− well and coupled to a last OTP anti-fuse cell and the bit line.