Controller and memory system
A controller includes an Error Correction Code (ECC) encoder adding a first parity to data to generate a data set, and encoding the data set to generate a first parity data set, a buffer temporarily storing the first parity data set, an ECC decoder decoding the first parity data set received from the buffer to generate a decoded data set, a first checker performing a Low Density Parity Check (LDPC) encoding on the decoded data set to generate an LDPC data set to which a second parity is added, and a second checker performing a syndrome check operation on the LDCP data set including the first and second parities.
1. A controller comprising:
an external cyclic redundancy check (ECRC) encoder configured to add a first parity to original data which is composed of a first bit number, and generate a first data set including the first parity and the original data, wherein the first data set is composed of a second bit number;
an encryption encoder configured to encrypt the first data set, and output a second data set which is composed of the second bit number;
an error correction code (ECC) encoder configured to add a second parity to the second data set by encoding, and generate a third data set which is composed of a third bit number greater than the second bit number;
a buffer configured to temporarily store the third data set;
an ECC decoder configured to decode the third data set received from the buffer, and generate a fourth data set which is composed of the third bit number;
a first checker configured to add a low density parity check (LDPC) parity to the fourth data set by LDPC encoding on the fourth data set, and generate a fifth data set which is composed of a fourth bit number greater than the third bit number; and
a second checker configured to perform a syndrome check operation on the fifth data set.
2. The controller of claim 1 , wherein the buffer includes a volatile memory or a non-volatile memory.
3. The controller of claim 1 , wherein the first checker performs the LDPC encoding by multiplying the fourth data set by a generation matrix.
4. The controller of claim 1 , wherein the second checker determines whether the syndrome check operation passes or fails according to a result of the syndrome check operation.
5. The controller of claim 4 , wherein the second checker performs the syndrome check operation by multiplying a parity check matrix by the fifth data set to calculate a syndrome vector.
6. The controller of claim 5 , wherein the second checker determines that the syndrome check operation passes when all bits of the syndrome vector are ‘0’, and that the syndrome check operation fails when at least one bit of ‘1’ is included in the syndrome vector.
7. The controller of claim 6 , wherein the second checker:
when the syndrome check operation passes, transfers the fifth data set to a memory device; and
when the syndrome check operation fails, searches for a check node value to make all bits of the syndrome vector become ‘0’.