IP Library › Granted Patent US 12,411,734
Granted Patent B2
US 12,411,734 · App. 18/602,031 · Granted Sep 9, 2025

Controller and memory system

Inventor: Do Hun Kim (Gyeonggi-do, KR)
Assignee: SK hynix Inc.
G06F11/1076G06F21/602H03M13/1102
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Quick Facts
Patent No.
US 12,411,734
App. No.
18/602,031
Granted
Sep 9, 2025
Kind
B2
Abstract

A controller includes an Error Correction Code (ECC) encoder adding a first parity to data to generate a data set, and encoding the data set to generate a first parity data set, a buffer temporarily storing the first parity data set, an ECC decoder decoding the first parity data set received from the buffer to generate a decoded data set, a first checker performing a Low Density Parity Check (LDPC) encoding on the decoded data set to generate an LDPC data set to which a second parity is added, and a second checker performing a syndrome check operation on the LDCP data set including the first and second parities.

Claims (51)

1. An operating method for a controller of a memory device, the method comprising:

receiving, from a host, a write request of data;

adding a parity to the data to obtain a first data set including the parity;

performing an ecc encoding operation to obtain a data set by adding an ecc parity to the first data set;

performing an ecc decoding operation on the data set;

performing an Idpc encoding operation by adding an Idpc parity to the first data set to obtain a second data set which includes the parity and the Idpc parity; and

transferring, to the memory device, the second data set according to a result of a syndrome check operation using the ecc parity on the second data set.

2. The method according to claim 1 ,

wherein the transferring the second data set comprises transferring the second data set when the syndrome check operation on the second data set passes.

3. The method according to claim 1 ,

wherein the transferring the second data set comprises searching for a check node value to make the syndrome check operation pass when the syndrome check operation on the second data set fails.

4. The method according to claim 1 , further comprising:

storing the data set in a buffer.

5. The method according to claim 4 , further comprising:

maintaining the data set in the buffer until the second data set is stored in the memory device.

6. The method according to claim 4 , wherein the buffer includes at least one of a volatile memory or a non-volatile memory.

7. The method according to claim 1 , further comprising:

encrypting the first data set using a Data Encryption Standard (DES) algorithm or an Advanced Encryption Standard (AES) algorithm.

8. The method according to claim 1 , wherein the parity is used for a cyclic redundancy check of data.

9. The method according to claim 1 , wherein the first data set is composed of a first bit number and the second data set is composed of a second bit number greater than the first bit number.

10. An operating method for a controller of a memory device, the method comprising:

receiving, from a host, a write request of data;

producing sets of data including a parity and a Idpc parity by performing an Idpc encoding operation;

transferring the sets of data to the memory device;

receiving, from the host, a read request of the data;

receiving, from the memory device, the sets of data;

restoring the data by performing an Idpc decoding operation;

transferring the data to the host,

wherein the producing sets of data comprises:

adding a parity to the data to obtain a first data set;

adding an ecc parity to the first data set to obtain a data set;

decoding the data set to remove the ecc parity from the data set;

encoding the data set to obtain a second data set which includes the parity and the Idpc parity; and

checking the second data set by performing a syndrome check operation using the ecc parity.

11. The method according to claim 10 ,

wherein the producing sets of data further comprises storing the data set in a buffer and maintaining the data set in the buffer until the sets of data are stored in the memory device.

12. The method according to claim 11 ,

wherein the producing sets of data further comprises encrypting the first data set using a Data Encryption Standard (DES) algorithm or an Advanced Encryption Standard (AES) algorithm.

13. The method according to claim 10 ,

wherein the parity is used for a cyclic redundancy check of data.

14. The method according to claim 10 , wherein the first data set is composed of a first bit number and the second data set is composed of a second bit number greater than the first bit number.

15. The method according to claim 10 ,

wherein the restoring the data by performing the Idpc decoding operation comprises:

performing the Idpc decoding operation on the sets of data to obtain decoded data by removing the Idpc parity;

performing an ecc encoding operation to obtain a data set by adding an ecc parity to the decoded data;

performing an ecc decoding operation on the data set by removing the ecc parity; and

performing a decoding operation to obtain the data by removing the parity from the decoded data.

16. The method according to claim 15 ,

wherein the restoring the data further comprises storing the data set in a buffer and maintaining the data set in the buffer until the transferring the data to the host is completed.

17. The method according to claim 15 ,

wherein the restoring the data further comprises decrypting the decoded data using a Data Encryption Standard (DES) algorithm or an Advanced Encryption Standard (AES) algorithm.

Priority Claims (1)
KR 10-2018-0168761 · Dec 24, 2018 · national
Continuity (4)
Continuation 17851130 · Jun 28, 2022
Continuation 17307129 · May 4, 2021
Division 16555264 · Aug 29, 2019
Related Publication 20240220363A1 · Jul 4, 2024
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