Integrated circuit package and method

1. A method comprising:

bonding a back side of a first integrated circuit die to a front side of a wafer;

depositing a first dielectric layer on the wafer and the first integrated circuit die;

planarizing the first dielectric layer such that surfaces of the first integrated circuit die and the first dielectric layer are planar;

forming a conductive via extending through the first dielectric layer, the conductive via being electrically coupled to the wafer without the use of solder; and

singulating the wafer and the first dielectric layer, singulated portions of the wafer forming a second integrated circuit die.

2. The method of claim 1 further comprising:

forming the first integrated circuit die, the first integrated circuit die comprising a first die connector; and

forming the second integrated circuit die in the wafer, the second integrated circuit die comprising a second die connector, the conductive via being physically and electrically coupled to the second die connector.

3. The method of claim 1 further comprising:

forming the first integrated circuit die, the first integrated circuit die comprising a first die connector; and

forming the second integrated circuit die in the wafer, the second integrated circuit die comprising a contact pad and a second dielectric layer over the contact pad, the conductive via extending through the second dielectric layer, the conductive via being physically and electrically coupled to the contact pad.

4. The method of claim 1 further comprising:

forming the first integrated circuit die, the first integrated circuit die comprising a contact pad and a second dielectric layer over the contact pad;

forming the second integrated circuit die in the wafer, the second integrated circuit die comprising a first die connector, the conductive via being physically and electrically coupled to the first die connector; and

after the bonding, forming a second die connector extending through the second dielectric layer, the second die connector being physically and electrically coupled to the contact pad.

5. The method of claim 1 further comprising:

forming the first integrated circuit die, the first integrated circuit die comprising a first contact pad and a second dielectric layer over the first contact pad; and

forming the second integrated circuit die in the wafer, the second integrated circuit die comprising a second contact pad and a third dielectric layer over the second contact pad, the conductive via extending through the third dielectric layer, the conductive via being physically and electrically coupled to the second contact pad; and

after the bonding, forming a die connector extending through the second dielectric layer, the die connector being physically and electrically coupled to the first contact pad.

6. The method of claim 1 further comprising:

forming a redistribution structure on the first integrated circuit die, the first dielectric layer, and the conductive via, the redistribution structure comprising metallization patterns, the metallization patterns being physically and electrically coupled to the conductive via and the first integrated circuit die.

7. The method of claim 6 , wherein the wafer and the first dielectric layer are singulated after forming the redistribution structure.

8. The method of claim 6 , wherein the wafer and the first dielectric layer are singulated before forming the redistribution structure.

9. The method of claim 1 , wherein the back side of the first integrated circuit die is bonded to the front side of the wafer with dielectric-to-dielectric bonds.

10. The method of claim 1 , wherein the back side of the first integrated circuit die is bonded to the front side of the wafer with an adhesive.

11. The method of claim 1 , wherein the first integrated circuit die comprises an alignment mark at the back side, and wherein bonding the back side of the first integrated circuit die to the front side of the wafer comprises:

placing the first integrated circuit die on the wafer while using the alignment mark for alignment; and

pressing the first integrated circuit die and the wafer together.

12. A method comprising:

encapsulating a die stack with an encapsulant, the die stack comprising:

a bottom integrated circuit die comprising a first die connector;

a top integrated circuit die on the bottom integrated circuit die, a back side of the top integrated circuit die being bonded to a front side of the bottom integrated circuit die, the bottom integrated circuit die being wider than the top integrated circuit die, the top integrated circuit die comprising a second die connector;

a first through via adjacent the top integrated circuit die, the first through via connected to the first die connector; and

a first dielectric layer surrounding the first through via and the top integrated circuit die, the first dielectric layer physically separating the first through via from the top integrated circuit die; and

forming a redistribution structure on the die stack and the encapsulant, the redistribution structure comprising a metallization pattern, the metallization pattern connecting the second die connector to the first through via.

13. The method of claim 12 further comprising forming the die stack without the use of solder, the top integrated circuit die being free from through substrate vias (TSVs).

14. The method of claim 13 , wherein forming the die stack comprises:

singulating the die stack before encapsulating the die stack, the bottom integrated circuit die and the first dielectric layer being laterally coterminous.

15. The method of claim 12 further comprising:

singulating the redistribution structure and the encapsulant, the redistribution structure and the encapsulant being laterally coterminous.

16. The method of claim 12 further comprising:

forming a conductive via over a carrier substrate; and

adhering the die stack to the carrier substrate,

wherein encapsulating the die stack with the encapsulant comprises forming the encapsulant around the die stack and the conductive via, top surfaces of the encapsulant, the first dielectric layer, the first through via, and the second die connector being planar.

17. The method of claim 12 , wherein forming the redistribution structure comprises forming the metallization pattern, the metallization pattern comprising conductive features having a pitch in a range of 0.8 μm to 5 μm.

18. A method comprising:

bonding a first integrated circuit die to a wafer with dielectric-to-dielectric bonds, the wafer comprising a second integrated circuit die;

forming a first dielectric layer around the first integrated circuit die;

forming a conductive via extending through the first dielectric layer, the conductive via being connected to the second integrated circuit die;

singulating the wafer to form a die stack comprising the first integrated circuit die and the second integrated circuit die; and

forming a redistribution structure on the die stack, the redistribution structure comprising metallization patterns, the metallization patterns connecting the first integrated circuit die to the second integrated circuit die.

19. The method of claim 18 further comprising:

forming an encapsulant around the die stack before forming the redistribution structure.

20. The method of claim 18 , wherein forming the redistribution structure comprises forming the metallization patterns, the metallization patterns comprising conductive features having a pitch in a range of 0.8 μm to 5 μm.