Integrated circuit and method of forming same and a system
An integrated circuit includes a first bit flip-flop and a second flip-flop. The first flip-flop has a first driving capability. The second flip-flop has a second driving capability different from the first driving capability. The first flip-flop and the second flip-flop are part of a multibit flip-flop configured to share at least a first clock pin. The first clock pin is configured to receive the first clock signal.
1. An integrated circuit comprising:
a first flip-flop having a first driving capability; and
a second flip-flop having a second driving capability different from the first driving capability,
wherein the first flip-flop and the second flip-flop are part of a multi-bit flip-flop configured to share at least a first clock pin configured to receive a first clock signal.
2. The integrated circuit of claim 1 , wherein
the first driving capability is based on the first flip-flop having a first threshold voltage; and
the second driving capability is based on the second flip-flop having a second threshold voltage.
3. The integrated circuit of claim 2 , wherein the first threshold voltage is different from the second threshold voltage.
4. The integrated circuit of claim 1 , wherein
the first driving capability is based on the first flip-flop having a first number of fins; and
the second driving capability is based on the second flip-flop having a second number of fins.
5. The integrated circuit of claim 4 , wherein the first number of fins is different from the second number of fins.
6. The integrated circuit of claim 1 , further comprising:
a third flip-flop having the first driving capability or the second driving capability,
wherein the third flip-flop is part of the multi-bit flip-flop and is configured to share the first clock pin with the first flip-flop and the second flip-flop.
7. The integrated circuit of claim 6 , further comprising:
a fourth flip-flop including a second clock pin configured to receive the first clock signal, the fourth flip-flop having a third driving capability different from the first driving capability or the second driving capability, the fourth flip-flop not being part of the multi-bit flip-flop.
8. The integrated circuit of claim 1 , wherein the first flip-flop and the second flip-flop are configured to share at least a pin configured to receive a signal.
9. The integrated circuit of claim 8 , wherein the signal includes at least an input signal, a set signal, a reset signal or a scan enable signal.
10. The integrated circuit of claim 8 , wherein the pin includes at least an input pin, a set pin, a reset pin or a scan enable pin.
11. A method of forming an integrated circuit (IC), the method comprising:
generating, by a processor, a standard cell layout of the integrated circuit, the generating of the standard cell layout comprising:
banking a first set of flip-flops into at least a first multi-bit flip-flop, each flip-flop in the first multi-bit flip-flop having a first driving current capability;
performing a first timing analysis of each flip-flop in the first multi-bit flip-flop; and
downsizing or upsizing a second set of flip-flops in at least the first multi-bit flip-flop, the second set of flip-flops having a second driving current capability different from the first driving current capability; and
manufacturing the integrated circuit based on the standard cell layout.
12. The method of claim 11 , wherein the downsizing or upsizing the second set of flip-flops in at least the first multi-bit flip-flop comprises:
upsizing the second set of flip-flops in at least the first multi-bit flip-flop, each flip-flop in the second set of flip-flops having a corresponding timing violation.
13. The method of claim 12 , wherein the generating of the standard cell layout further comprises:
performing a second timing analysis of each flip-flop in the second set of flip-flops.
14. The method of claim 11 , wherein the downsizing or upsizing the second set of flip-flops in at least the first multi-bit flip-flop comprises:
downsizing the second set of flip-flops in at least the first multi-bit flip-flop, each flip-flop in the second set of flip-flops not having a corresponding timing violation.
15. The method of claim 14 , wherein the generating of the standard cell layout further comprises:
performing a second timing analysis of each flip-flop in the second set of flip-flops.
16. The method of claim 11 , wherein
the first driving current capability is based on the first set of flip-flops having a first threshold voltage,
the second driving current capability is based on the second set of flip-flops having a second threshold voltage, and
the first threshold voltage is different from the second threshold voltage.
17. The method of claim 11 , wherein
the first driving current capability is based on the first set of flip-flops having a first number of fins,
the second driving current capability is based on the second set of flip-flops having a second number of fins, and
the first number of fins is different from the second number of fins.
18. A system for designing an integrated circuit, the system comprises:
a non-transitory computer readable medium configured to store executable instructions; and
a processor coupled to the non-transitory computer readable medium, wherein the processor is configured to execute the instructions for:
banking a first set of flip-flops into at least a first multi-bit flip-flop, each flip-flop in the first multi-bit flip-flop having a first driving current capability;
performing a first timing analysis of each flip-flop in the first multi-bit flip-flop; and
downsizing or upsizing a second set of flip-flops in at least the first multi-bit flip-flop, the second set of flip-flops having a second driving current capability different from the first driving current capability.
19. The system of claim 18 , wherein the processor is configured to execute instructions where
the first driving current capability is based on the first set of flip-flops having a first threshold voltage,
the second driving current capability is based on the second set of flip-flops having a second threshold voltage, and
the first threshold voltage is different from the second threshold voltage.
20. The system of claim 18 , wherein the processor is configured to execute instructions where
the first driving current capability is based on the first set of flip-flops having a first number of fins,
the second driving current capability is based on the second set of flip-flops having a second number of fins, and
the first number of fins is different from the second number of fins.