IP Library › Granted Patent US 12,400,067
Granted Patent B2
US 12,400,067 · App. 18/746,888 · Granted Aug 26, 2025

Integrated circuit and method of forming same and a system

Inventors: Sheng-Hsiung Chen (Hsinchu, TW); Wen-Hao Chen (Hsinchu, TW); Hung-Chih Ou (Hsinchu, TW); Chun-Yao Ku (Hsinchu, TW); Shao-Huan Wang (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
G06F30/398G06F30/3315G06F30/337G06F30/396G06F30/392G06F2115/06G06F2119/06G06F2119/12
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Quick Facts
Patent No.
US 12,400,067
App. No.
18/746,888
Granted
Aug 26, 2025
Kind
B2
Abstract

A multi-bit flip-flop includes a first flip-flop and a second flip-flop. The first flip-flop has a first driving capability. The first flip-flop includes a first set pin configured to receive a first set signal. The second flip-flop has a second driving capability different from the first driving capability. The second flip-flop includes a second set pin configured to receive the first set signal, and the first set pin and the second set pin are coupled together. The first flip-flop and the second flip-flop are configured to share at least a first clock pin.

Claims (66)

1. A multi-bit flip-flop comprising:

a first flip-flop having a first driving capability, the first flip-flop including a first set pin configured to receive a first set signal; and

a second flip-flop having a second driving capability different from the first driving capability, the second flip-flop including a second set pin configured to receive the first set signal, and the first set pin and the second set pin are coupled together,

wherein the first flip-flop and the second flip-flop are configured to share at least a first clock pin.

2. The multi-bit flip-flop of claim 1 , further comprising:

a third flip-flop having the first driving capability, the third flip-flop including a third set pin configured to receive the first set signal, and the third set pin being coupled to the first set pin and the second set pin,

wherein the third flip-flop is configured to share the first clock pin with the first flip-flop and the second flip-flop.

3. The multi-bit flip-flop of claim 2 , further comprising:

a fourth flip-flop having the second driving capability, the fourth flip-flop including a fourth set pin configured to receive the first set signal, and the fourth set pin being coupled to the first set pin, the second set pin and the third set pin,

wherein the fourth flip-flop is configured to share the first clock pin with the first flip-flop, the second flip-flop and the third flip-flop.

4. The multi-bit flip-flop of claim 1 , wherein

the first driving capability is based on the first flip-flop having a first number of fins; and

the second driving capability is based on the second flip-flop having a second number of fins.

5. The multi-bit flip-flop of claim 4 , wherein the first number of fins is different from the second number of fins.

6. The multi-bit flip-flop of claim 1 , wherein

the first driving capability is based on the first flip-flop having a first threshold voltage; and

the second driving capability is based on the second flip-flop having a second threshold voltage.

7. The multi-bit flip-flop of claim 6 , wherein the first threshold voltage is different from the second threshold voltage.

8. The multi-bit flip-flop of claim 1 , wherein

the first flip-flop further includes a first data input pin configured to receive a first data signal; and

the second flip-flop further includes a second data input pin configured to receive a second data signal.

9. The multi-bit flip-flop of claim 8 , wherein

the first flip-flop further includes:

a first reset pin configured to receive a first reset signal; and

the second flip-flop further includes:

a second reset pin configured to receive the first reset signal, and the first reset pin and the second reset pin are coupled together.

10. The multi-bit flip-flop of claim 1 , wherein at least one of the first flip-flop or the second flip-flop is an SR flip-flop, a DQ flip-flop, JK flip-flop or a T-flip-flop.

11. A method of forming an integrated circuit, the method comprising:

placing, by a processor, a standard cell of the integrated circuit, the placing of the standard cell comprising:

determining if a first multi-bit flip-flop (MBFF) had a first timing violation, the first MBFF includes a first set of flip-flops, each flip-flop in the first set of flip-flops having a first driving current capability;

upsizing a second set of flip-flops in at least the first MBFF in response to determining that the first MBFF had the first timing violation, the second set of flip-flops having a second driving current capability different from the first driving current capability; and

manufacturing the integrated circuit based on the standard cell.

12. The method of claim 11 , wherein each flip-flop in the second set of flip-flops has a corresponding timing violation.

13. The method of claim 11 , further comprising:

determining if the first MBFF had a second timing violation; and

upsizing a third set of flip-flops in the second set of flip-flops in at least the first MBFF in response to determining that the first MBFF had the second timing violation,

wherein the third set of flip-flops have a third driving current capability different from the first driving current capability and the second driving current capability, and

each flip-flop in the third set of flip-flops has a corresponding timing violation.

14. The method of claim 11 , wherein

each flip-flop in the first multi-bit flip-flop with the first driving current capability has a first number of fins,

each flip-flop in the second set of flip-flops has a second number of fins, and

the first number of fins is different from the second number of fins.

15. The method of claim 11 , wherein

each flip-flop in the first multi-bit flip-flop with the first driving current capability has a first threshold voltage,

each flip-flop in the second set of flip-flops has a second threshold voltage, and

the first threshold voltage is different from the second threshold voltage.

16. A system for designing an integrated circuit, the system comprises:

a non-transitory computer readable medium configured to store non-transitory instructions; and

a processor coupled to the non-transitory computer readable medium, wherein the processor is configured to execute the non-transitory instructions for:

determining if a first multi-bit flip-flop (MBFF) had a first timing violation, the first MBFF includes a first set of flip-flops, each flip-flop in the first set of flip-flops having a first driving current capability; and

upsizing a second set of flip-flops in at least the first MBFF in response to determining that the first MBFF had the first timing violation, the second set of flip-flops having a second driving current capability different from the first driving current capability.

17. The system of claim 16 , wherein the processor is configured to execute the non-transitory instructions where

the first driving current capability is based on the first set of flip-flops having a first number of fins,

the second driving current capability is based on the second set of flip-flops having a second number of fins, and

the first number of fins is different from the second number of fins.

18. The system of claim 16 , wherein the processor is configured to execute the non-transitory instructions where

the first driving current capability is based on the first set of flip-flops having a first threshold voltage,

the second driving current capability is based on the second set of flip-flops having a second threshold voltage, and

the first threshold voltage is different from the second threshold voltage.

19. The system of claim 16 , wherein the processor is configured to execute the non-transitory instructions where

each flip-flop in the second set of flip-flops has a corresponding first timing violation.

20. The system of claim 16 , wherein the processor is configured to execute the non-transitory instructions further comprising:

determining if the first MBFF had a second timing violation; and

upsizing a third set of flip-flops in the second set of flip-flops in at least the first MBFF in response to determining that the first MBFF had the second timing violation,

wherein the third set of flip-flops have a third driving current capability different from the first driving current capability and the second driving current capability, and

each flip-flop in the third set of flip-flops has a corresponding second timing violation.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 18, 2024
From: CHEN, SHENG-HSIUNG; WANG, SHAO-HUAN; CHEN, WEN-HAO; KU, CHUN-YAO; OU, HUNG-CHIH
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 067760/0350 →
Continuity (6)
Continuation 18337245 · Jun 19, 2023
Continuation 17692767 · Mar 11, 2022
Continuation 17235262 · Apr 20, 2021
Continuation 16559534 · Sep 3, 2019
Provisional Application 62733878 · Sep 20, 2018
Related Publication 20240338511A1 · Oct 10, 2024
References Cited (42)
US 7260442B2 · Hwang et al. · 2007 [cited by applicant]
US 9177096B2 · Sundareswaran et al. · 2015 [cited by applicant]
US 9256709B2 · Yu et al. · 2016 [cited by applicant]
US 9361417B2 · Arunachalam et al. · 2016 [cited by applicant]
US 9513658B2 · Krishnamurthy et al. · 2016 [cited by applicant]
US 9667230B1 · Fojtik et al. · 2017 [cited by applicant]
US 9779197B1 · Wagner · 2017 [cited by examiner]
US 10338139B1 · Ge et al. · 2019 [cited by applicant]
US 10641822B2 · Balasbrumanian et al. · 2020 [cited by applicant]
US 10958252B2 · Wu et al. · 2021 [cited by applicant]
US 10990745B2 · Chen et al. · 2021 [cited by applicant]
US 11275886B2 · Chen et al. · 2022 [cited by applicant]
US 11681853B2 · Chen · 2023 [cited by applicant]
US 12014131B2 · Chen · 2024 [cited by examiner]
US 20030014612A1 · Joy et al. · 2003 [cited by applicant]
US 20140040838A1 · Liu et al. · 2014 [cited by applicant]
US 20150227646A1 · Arunachalam et al. · 2015 [cited by applicant]
US 20150278429A1 · Chang · 2015 [cited by applicant]
US 20150318845A1 · Pasternak · 2015 [cited by applicant]
US 20160241219A1 · Kim et al. · 2016 [cited by applicant]
US 20160266604A1 · Krishnamurthy et al. · 2016 [cited by applicant]
US 20170045576A1 · Balasubramanian et al. · 2017 [cited by applicant]
US 20170063350A1 · Cheng et al. · 2017 [cited by applicant]
US 20170292993A1 · Yoon et al. · 2017 [cited by applicant]
US 20180131351A1 · Lee et al. · 2018 [cited by applicant]
CN 105897221 · 2016 [cited by applicant]
CN 108092660 · 2018 [cited by applicant]
JP 2007173509 · 2007 [cited by applicant]
JP 2013182600 · 2013 [cited by applicant]
TW 201630352 · 2016 [cited by applicant]
R.P. Pokala et al., “Physical Synthesis for Performance Optimization,” Fifth Annual IEEE International ASIC Conference and Exhibit, Sep. 1992, pp. 34-37. DOI: 10.1109/ASIC.1992.270312 (Year: 1992). [cited by applicant]
S.-H. Wang et al., “Power-Driven Flip-Flop Merging and Relocation,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 31, No. 2, Feb. 2012, pp. 180-191. (Year: 2012). [cited by applicant]
G. Barathi et al., “Lower Power High Speed Memory Architecture Using Multi-bit Flip-Flops,” Int'l Journal of Advanced Information Science and Technology (IJAIST), vol. 13, No. 13, May 2013, pp. 117-126. (Year: 2013). [cited by applicant]
C.-C. Lu et al., “Slack Budgeting and Slack to Length Converting for Multi-bit Flip-Flop Merging,” 2013 EDAA, IEEE, 6 pages. (Year: 2013). [cited by applicant]
S. Sharma et al., “Shift Register Design Using Two Bit Flip-Flop,” Proc. of 2014 RAECS UIET Panjab University Chandigarh, IEEE, 5 pages. (Year: 2014). [cited by applicant]
A. Abinaya et al., “Efficient Flip-Flop Merging Technique for Clock Power Reduction,” IEEE Sponsored 2nd Int'l Conference on Electronics and Communication System (ICECS 2015), pp. 326-330. (Year: 2015). [cited by applicant]
D. Gluzer et al., “Probability-Driven Multibit Flip-Flop Integration With Clock Gating,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 25, No. 3, Mar. 2017, pp. 1173-1177. (Year 2017). [cited by applicant]
Office Action dated Jan. 7, 2022 for corresponding case No. TW 11120031400. (pp. 1-4). [cited by applicant]
Xunji, Zheng, “Research on Digital Circuits Low Power Design Method Based on Multi Bit Flip Flop”, A thesis submitted to Xidian University; May 2017, 77 pages. [cited by applicant]
Xinjie, Wang, “SoC Low Power Design and Implementation Based on Multi-Bit Flip Flop”, A thesis submitted to Graduate School of National University of Defense Technology Changsha, Hunan, P.R. China, Mar. 2015, 87 pages. [cited by applicant]
Santos, Cristiano et al., “Multi-Bit Flip-Flop Usage Impact on Physical Synthesis”, State Intellectual Property Office of China, Donwloaded on Mar. 18, 2024, IEEE Xplore, 6 pages. [cited by applicant]
“Research on Low Power Technology Based on Multi-Bit Flip Flop” 71 pages. [cited by applicant]