Integrated circuit and method of forming same and a system
A multi-bit flip-flop includes a first flip-flop, a second flip-flop and a first inverter. The first flip-flop has a first driving capability. The second flip-flop has a second driving capability different from the first driving capability. The first inverter is configured to receive a first clock signal on a first clock pin, and is configured to generate a second clock signal inverted from the first clock signal. The first flip-flop and the second flip-flop are configured to share at least the first clock pin.
1. A multi-bit flip-flop comprising:
a first flip-flop having a first driving capability;
a second flip-flop having a second driving capability different from the first driving capability; and
a first inverter configured to receive a first clock signal on a first clock pin, and configured to generate a second clock signal inverted from the first clock signal;
wherein the first flip-flop and the second flip-flop are configured to share at least the first clock pin.
2. The multi-bit flip-flop of claim 1 , further comprising:
a third flip-flop having the first driving capability or the second driving capability,
wherein the third flip-flop is configured to share the first clock pin with the first flip-flop and the second flip-flop.
3. The multi-bit flip-flop of claim 2 , further comprising:
a fourth flip-flop including a second clock pin configured to receive the first clock signal, the fourth flip-flop having a third driving capability different from the first driving capability or the second driving capability, the fourth flip-flop not being part of the multi-bit flip-flop.
4. The multi-bit flip-flop of claim 1 , wherein at least one of the first flip-flop or the second flip-flop is a JK flip-flop, a T-flip-flop, an SR flip-flop or a DQ flip-flop.
5. The multi-bit flip-flop of claim 1 , wherein
the first flip-flop includes:
a first reset pin configured to receive a first reset signal; and
a first set pin configured to receive a first set signal; and
the second flip-flop includes:
a second reset pin configured to receive the first reset signal, and the first reset pin and the second reset pin are coupled together; and
a second set pin configured to receive the first set signal, and the first set pin and the second set pin are coupled together.
6. The multi-bit flip-flop of claim 1 , wherein
the first flip-flop includes a first data input pin configured to receive a first data signal; and
the second flip-flop includes a second data input pin configured to receive a second data signal.
7. The multi-bit flip-flop of claim 1 , wherein
the first driving capability is based on the first flip-flop having a first threshold voltage; and
the second driving capability is based on the second flip-flop having a second threshold voltage.
8. The multi-bit flip-flop of claim 7 , wherein the first threshold voltage is different from the second threshold voltage.
9. The multi-bit flip-flop of claim 1 , wherein
the first driving capability is based on the first flip-flop having a first number of fins; and
the second driving capability is based on the second flip-flop having a second number of fins.
10. The multi-bit flip-flop of claim 9 , wherein the first number of fins is different from the second number of fins.
11. A method of forming an integrated circuit (IC), the method comprising:
generating, by a processor, a standard cell layout of the integrated circuit, the generating of the standard cell layout comprising:
performing a first timing analysis of a first multi-bit flip-flop, the first multi-bit flip-flop includes a first set of flip-flops, each flip-flop in the first set of flip-flops having a first driving current capability;
downsizing a second set of flip-flops in at least the first multi-bit flip-flop in response to performing the first timing analysis, the second set of flip-flops having a second driving current capability different from the first driving current capability; and
performing a second timing analysis of each flip-flop in the second set of flip-flops; and
manufacturing the integrated circuit based on the standard cell layout.
12. The method of claim 11 , wherein each flip-flop in the second set of flip-flops does not have a corresponding timing violation in the first timing analysis.
13. The method of claim 11 , wherein
each flip-flop in the first multi-bit flip-flop with the first driving current capability has a first number of fins,
each flip-flop in the second set of flip-flops has a second number of fins, and
the first number of fins is different from the second number of fins.
14. The method of claim 11 , wherein
each flip-flop in the first multi-bit flip-flop with the first driving current capability has a first threshold voltage,
each flip-flop in the second set of flip-flops has a second threshold voltage, and
the first threshold voltage is different from the second threshold voltage.
15. The method of claim 11 , further comprising:
downsizing a third set of flip-flops in the second set of flip-flops in response to performing the second timing analysis,
wherein each flip-flop in the third set of flip-flops did not have a corresponding timing violation in the second timing analysis.
16. A system for designing an integrated circuit, the system comprises:
a non-transitory computer readable medium configured to store non-transitory instructions; and
a processor coupled to the non-transitory computer readable medium, wherein the processor is configured to execute the non-transitory instructions comprising:
performing a first timing analysis of a first multi-bit flip-flop, the first multi-bit flip-flop includes a first set of flip-flops, each flip-flop in the first set of flip-flops having a first driving current capability;
downsizing a second set of flip-flops in at least the first multi-bit flip-flop in response to performing the first timing analysis, the second set of flip-flops having a second driving current capability different from the first driving current capability; and
performing a second timing analysis of each flip-flop in the second set of flip- flops.
17. The system of claim 16 , wherein the processor is configured to execute the non-transitory instructions where
each flip-flop in the second set of flip-flops does not have a corresponding timing violation in the first timing analysis.
18. The system of claim 16 , wherein the processor is configured to execute the non-transitory instructions further comprising:
downsizing a third set of flip-flops in the second set of flip-flops in response to performing the second timing analysis,
wherein each flip-flop in the third set of flip-flops did not have a corresponding timing violation in the second timing analysis.
19. The system of claim 16 , wherein the processor is configured to execute the non-transitory instructions where
the first driving current capability is based on the first set of flip-flops having a first number of fins,
the second driving current capability is based on the second set of flip-flops having a second number of fins, and
the first number of fins is different from the second number of fins.
20. The system of claim 16 , wherein the processor is configured to execute the non-transitory instructions where
the first driving current capability is based on the first set of flip-flops having a first threshold voltage,
the second driving current capability is based on the second set of flip-flops having a second threshold voltage, and
the first threshold voltage is different from the second threshold voltage.