IP Library › Granted Patent US 9,361,417
Granted Patent B2
US 9,361,417 · App. 14/192,413 · Granted Jun 7, 2016

Placement of single-bit and multi-bit flip-flops

Inventors: Anand Arunachalam (Sunnyvale, CA); Suman Chatterjee (Bengaluru, IN); Jing C. Lin (Cupertino, CA)
Assignee: Synopsys, Inc.
G06F17/5072
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Quick Facts
Patent No.
US 9,361,417
App. No.
14/192,413
Granted
Jun 7, 2016
Kind
B2
Abstract

Technology is disclosed for placement of single-bit flip-flops and multi-bit flip-flops. Single-bit flip-flops with replaced with multi-bit flip-flops and/or relative placement groups of single-bit flip-flops.

Claims (46)

1. A method of circuit design in an integrated circuit EDA flow for lithographic masks for production of integrated circuits with a computer system, comprising:

generating with the computer system a placed, routed, and optimized circuit design in the integrated circuit EDA flow for lithographic masks for production of integrated circuits, including:

with the computer system, performing a first placement for a netlist of the circuit design according to a first set of circuit element positioning rules;

with the computer system, identifying a plurality of single-bit flip-flops in the circuit design including at least a first set of single-bit flip-flops and a second set of single-bit flip-flops;

with the computer system, grouping the second set of single-bit flip-flops together as a first relative placement set of single-bit flip-flops, and replacing the first set of single-bit flip-flops in the circuit design with at least a first set of multi-bit flip-flops in the circuit design;

with the computer system, creating a second set of circuit element positioning rules for the first relative placement set of single-bit flip-flops based on a result of the first placement, the second set of circuit element positioning rules specifying positioning of the first relative placement set of single-bit flip-flops;

responsive to a design success with the first relative placement set of single-bit flip-flops in the circuit design, replacing the first relative placement set of single-bit flip-flops in the circuit design, with at least a second set of multi-bit flip-flops in the circuit design; and

with the computer system, completing placement, routing, and optimization of the netlist of the circuit design according to the second set of circuit element positioning rules.

2. The method of claim 1 , further comprising:

responsive to a design failure with the first set of multi-bit flip-flops in the circuit design, replacing the first set of multi-bit flip-flops in the circuit design, with at least a second relative placement set of single-bit flip-flops in the circuit design.

3. The method of claim 1 , further comprising:

responsive to a design failure with the first set of multi-bit flip-flops in the circuit design, replacing the first set of multi-bit flip-flops in the circuit design, with at least a second set of multi-bit flip-flops in the circuit design, wherein multi-bit flip-flops in the second set of multi-bit flip-flops have fewer inputs per flip-flop than in the first set of multi-bit flip-flops in the circuit design.

4. The method of claim 1 , further comprising:

responsive to a design failure with the first set of multi-bit flip-flops in the circuit design, replacing the first set of multi-bit flip-flops in the circuit design, with at least (i) a second set of multi-bit flip-flops in the circuit design and (ii) a third set of single-bit flip flops, wherein multi-bit flip-flops in the second set of multi-bit flip-flops have fewer inputs per flip-flop than in the first set of multi-bit flip-flops in the circuit design.

5. The method of claim 1 , further comprising:

responsive to a design failure with the first set of multi-bit flip-flops in the circuit design, replacing the first set of multi-bit flip-flops in the circuit design, with at least (i) a second set of multi-bit flip-flops in the circuit design and (ii) a second relative placement set of single-bit flip flops, wherein multi-bit flip-flops in the second set of multi-bit flip-flops having fewer inputs per flip-flop than in the first set of multi-bit flip-flops in the circuit design.

6. The method of claim 1 , further comprising:

responsive to the design success with the first relative placement set of single-bit flip-flops in the circuit design, in addition to replacing the first relative placement set of single-bit flip-flops in the circuit design with at least the second set of multi-bit flip-flops in the circuit design, replacing the first relative placement set of single-bit flip-flops in the circuit design, with at least a third set of single-bit flip-flops in the circuit design.

7. The method of claim 1 , further comprising:

responsive to the design success with the first relative placement set of single-bit flip-flops in the circuit design, in addition to replacing the first relative placement set of single-bit flip-flops in the circuit design with at least the second set of multi-bit flip-flops in the circuit design, replacing the first relative placement set of single-bit flip-flops in the circuit design, with at least a second relative placement set of single-bit flip-flops in the circuit design.

8. A method of circuit design in an integrated circuit EDA flow for lithographic masks for production of integrated circuits with a computer system, comprising:

generating with the computer system a placed, routed, and optimized circuit design in the integrated circuit EDA flow for lithographic masks for production of integrated circuits, including:

with the computer system, performing a first placement for a netlist of the circuit design according to a first set of circuit element positioning rules;

with the computer system, identifying a plurality of single-bit flip-flops in the circuit design including at least a first relative placement set of single-bit flip-flops;

with the computer system, creating a second set of circuit element positioning rules for the first relative placement set of single-bit flip-flops based on a result of the first placement, the rules specifying positioning of the first relative placement set of single-bit flip-flops;

with the computer system, replacing the first relative placement set of single-bit flip-flops in the circuit design with at least a first set of multi-bit flip-flops in the circuit design; and

responsive to a design failure with the first set of multi-bit flip-flops in the circuit design, replacing the first set of multi-bit flip-flops in the circuit design, with at least a second relative placement set of single-bit flip-flops in the circuit design.

9. The method of claim 8 , wherein

said replacing includes, replacing the first relative placement set of single-bit flip-flops in the circuit design with at least (i) the first set of multi-bit flip-flops in the circuit design and (ii) a set of single-bit flip-flops.

10. The method of claim 8 , wherein

said replacing includes, replacing the first relative placement set of single-bit flip-flops in the circuit design with at least (i) the first set of multi-bit flip-flops in the circuit design and (ii) a second relative placement set of single-bit flip-flops.

11. The method of claim 8 , wherein multi-bit flip-flops in the second set of multi-bit flip-flops have fewer inputs per flip-flop than in the first set of multi-bit flip-flops in the circuit design.

12. A method of circuit design in an integrated circuit EDA flow for lithographic masks for production of integrated circuits with a computer system, comprising:

generating with the computer system a placed, routed, and optimized circuit design in the integrated circuit EDA flow for lithographic masks for production of integrated circuits, including:

with the computer system, performing a first placement for a netlist of the circuit design according to a first set of circuit element positioning rules;

with the computer system, identifying a plurality of flip-flops in the circuit design including at least a first set of multi-bit flip-flops;

with the computer system, replacing the first set of multi-bit flip-flops in the circuit design with a first relative placement set of single-bit flip-flops in the circuit design; and

with the computer system, creating a second set of circuit element positioning rules for the first relative placement set of single-bit flip-flops based on a result of the first placement, the rules specifying positioning of the first relative placement set of single-bit flip-flops.

13. The method of claim 12 , wherein

said replacing the first set of multi-bit flip-flops in the circuit design, with at least the first relative placement set of single-bit flip-flops in the circuit design, is responsive to a design failure with the first set of multi-bit flip-flops in the circuit design.

14. The method of claim 12 , further comprising:

responsive to a design success with the first relative placement set of single-bit flip-flops in the circuit design, replacing the first relative placement set of single-bit flip-flops in the circuit design, with at least a second set of multi-bit flip-flops in the circuit design.

15. The method of claim 12 , further comprising:

responsive to a design success with the first relative placement set of single-bit flip-flops in the circuit design, replacing the first relative placement set of single-bit flip-flops in the circuit design, with at least (i) a second set of multi-bit flip-flops in the circuit design and (ii) a set of single-bit flip-flops in the circuit design.

16. The method of claim 12 , further comprising:

responsive to a design success with the first relative placement set of single-bit flip-flops in the circuit design, replacing the first relative placement set of single-bit flip-flops in the circuit design, with at least (i) a second set of multi-bit flip-flops in the circuit design and (ii) a second relative placement set of single-bit flip-flops in the circuit design.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 7, 2014
From: ARUNACHALAM, ANAND; CHATTERJEE, SUMAN; LIN, JING C.
To: SYNOPSYS, INC.
Reel/Frame 032619/0426 →
Continuity (2)
Provisional Application 61937104 · Feb 7, 2014
Related Publication 20150227646A1 · Aug 13, 2015