Semiconductor device having deep trench structure and method of manufacturing thereof
A semiconductor device includes etch stop films formed on the first gate electrode, the first source region, the first drain region, and the shallow trench isolation regions, respectively. First interlayer insulating films are formed on the etch stop film, respectively. Deep trenches are formed in the substrate between adjacent ones of the first interlayer insulating films to overlap the shallow trench isolation regions. Sidewall insulating films are formed in the deep trenches, respectively. A gap-fill insulating film is formed on the sidewall insulating film. A second interlayer insulating film is formed on the gap-fill insulating film. A top surface of the second interlayer insulating film is substantially planar and a bottom surface of the second interlayer insulating film is undulating.
1. A method of manufacturing a semiconductor device, the method comprising:
forming shallow trench isolation regions on a substrate;
forming a first gate electrode, a first source region, and a first drain region between the shallow trench isolation regions;
forming an etch stop film on a surface of the substrate;
depositing a first interlayer insulating film on the etch stop film;
forming first photoresist patterns on the first interlayer insulating film;
etching the first interlayer insulating film exposed between adjacent ones of the first photoresist patterns and the etch stop film to expose the substrate;
removing the first photoresist patterns;
etching the exposed substrate using the first interlayer insulating film as a mask to form a plurality of deep trenches;
depositing a sidewall insulating film on sidewalls of the deep trench;
depositing a gap-fill insulating film on the sidewall insulating film;
depositing a second interlayer insulating film on the gap-fill insulating film;
forming second photoresist patterns on portions of the second interlayer insulating film overlapping the plurality of deep trenches;
performing etch-back processing on the second interlayer insulating film region between adjacent ones of the second photoresist patterns;
removing the second photoresist patterns;
performing chemical mechanical polishing (CMP) processing on the second interlayer insulating film to form a planarized second interlayer insulating film;
depositing a third interlayer insulating film on the planarized second interlayer insulating film;
forming a contact plug connected to the first source region or the first drain region; and
forming a metal wiring connected to the contact plug.
2. The method of claim 1 , wherein the gap-fill insulating film and the second interlayer insulating film comprise a borophosphosilicate glass (BPSG) film.
3. The method of claim 1 , wherein the contact plug is formed by etching the etch stop film, the first, second, and third interlayer insulating films.
4. The method of claim 1 , wherein the first interlayer insulating film has an uneven surface, and
wherein a top surface of the planarized second interlayer insulating film is smoother than a surface of the first interlayer insulating film.
5. The method of claim 1 further comprising:
forming a first buried layer in a first region of the substrate; and
forming a second buried layer, a drift region, and a body region on the first buried layer,
wherein one of the shallow trench isolation regions overlaps the first gate electrode.
6. The method of claim 1 further comprising:
forming a second gate electrode in the substrate;
performing ion implantation using the second gate electrode to form a well region in the substrate; and
forming a second source region and a second drain region in the well region,
wherein a depth of the well region under the second gate electrode is smaller than a depth of the well region under the second source region or the second drain region.
7. The method of claim 1 , wherein an ion implantation process is performed after the forming the plurality of deep trenches to form a channel stop layer.