Detection and correction of single event upset (SEU) in integrated circuit

1. A fault suppression method, comprising:

receiving by a latching circuit an input signal, a data signal and a clear signal;

outputting by the latching circuit a first voltage level at an output of the latching circuit; and

generating a function control signal holding the first voltage level outputted by the latching circuit, including:

detecting a single event upset that originates within the latching circuit and causes the first voltage level at the output of the latching circuit to transition to a second voltage level;

in response to detection of the single event upset, controlling the latching circuit via the clear signal to reset the output of the latching circuit to the first voltage level, wherein a glitch is formed on the first voltage level at the output of the latching circuit in response to the single event upset; and

suppressing the glitch at the output of the latching circuit to generate the function control signal holding the first voltage level without the glitch.

2. The method of claim 1 , further comprising:

outputting the second voltage level at the output of the latching circuit; and

detecting a clear event in the clear signal, wherein the first voltage level is outputted at the output of the latching circuit in place of the second voltage level in response to the clear event.

3. The method of claim 1 , further comprising:

detecting a trigger event in the data signal received by the latching circuit; and

in response to detection of the trigger event in the data signal:

controlling the latching circuit to sample the input signal at a first time; and

refreshing the function control signal to hold the second voltage level corresponding to the input signal sampled at the first time.

4. The method of claim 3 , wherein the trigger event corresponds to a first edge of the data signal, further comprising:

holding the second voltage level at the output of the latching circuit until detecting a clear event in the clear signal or until detecting a second edge in the data signal subsequent to the first edge.

5. The method of claim 4 , wherein the first and second edges are rising edges of the data signal.

6. The method of claim 4 , wherein one of the first and second edges is a falling edged of the data signal, and the other of the first and second edges is a rising edge of the data signal.

7. The method of claim 3 , wherein the trigger event corresponds to the data signal being biased at the second voltage level, further comprising:

tracking the input signal at the output of the latching circuit while the data signal is biased at the second voltage level.

8. The method of claim 1 , further comprising controlling a core function according to the function control signal, including:

when the function control signal holds the first voltage level, monitoring an electrical characteristic associated with the core function;

detecting an abnormal event based on the electrical characteristic associated with the core function;

outputting the data signal including a trigger event associated with the abnormal event;

in response to the trigger event of the data signal, refreshing the latching circuit to latch a voltage level of the input signal at the output of the latching circuit; and

refreshing the function control signal based on the output of the latching circuit.

9. The method of claim 1 , wherein the first voltage level is lower than the second voltage level.

10. The method of claim 1 , wherein the input signal is constantly coupled to the second voltage level.

11. The method of claim 1 , wherein:

the clear signal includes a pulse corresponding to the single event upset and the glitch on the first voltage level held at the output of the latching circuit; and

the pulse of the clear signal has a pulse width configured to be greater than a duration of the glitch.

12. The method of claim 11 , further comprising:

estimating durations of glitch pulses associated with the latching circuit; and

programming the pulse width based on the estimated durations.

13. The method of claim 11 , further comprising, while delaying the output of the latching circuit for outputting via the function control signal:

in accordance with a determination of operating within the pulse of the clear signal, selecting the first voltage level to be outputted to the function control signal; and

in accordance with a determination of operating outside the pulse of the clear signal, selecting the delayed output of the latching circuit to be outputted via the function control signal.

14. An electronic device, comprising:

a latching circuit configured to receive an input signal, a data signal and a clear signal and be controlled by the data signal to hold a first voltage level at an output;

a fault detection circuit coupled to the latching circuit, the fault detection circuit being configured to detect a single event upset that originates within the latching circuit and causes the first voltage level at the output of the latching circuit to transition to a second voltage level;

a fault clear circuit coupled between the fault detection circuit and the latching circuit, the fault clear circuit being configured to generate the clear signal in response to detection of the single event upset and control the latching circuit to reset the output of the latching circuit to the first voltage level, wherein a glitch is formed on the first voltage level at the output of the latching circuit in response to the single event upset; and

an output control circuit coupled to the latching circuit, the output control circuit being configured to suppress the glitch at the output of the latching circuit and generate a function control signal holding the first voltage level without the glitch.

15. The electronic device of claim 14 , wherein the input signal is constantly coupled to the second voltage level.

16. The electronic device of claim 14 , wherein:

the clear signal includes a pulse corresponding to the single event upset and the glitch on the first voltage level held at the output of the latching circuit; and

the pulse of the clear signal has a pulse width configured to be greater than a duration of the glitch.

17. The electronic device of claim 14 , wherein the output control circuit further includes a filter configured to filter out the glitch.

18. A single event upset (SEU) suppression method, comprising:

receiving by a D-type flip flop (DFF) an input signal, a data signal and a clear signal;

outputting by the DFF a first voltage level at an output of the DFF;

generate a function control signal holding the first voltage level outputted by the DFF, including:

detecting a single event upset that originates within the DFF and causes the first voltage level at the output of the DFF to transition to a second voltage level;

in response to detection of the single event upset, controlling the DFF via the clear signal to reset the output of the DFF to the first voltage level, wherein a glitch is formed on the first voltage level at the output of the DFF in response to the single event upset; and

suppressing the glitch at the output of the DFF to generate the function control signal holding the first voltage level without the glitch.

19. The method of claim 18 , further comprising:

outputting the second voltage level at the output of the DFF; and

detecting a clear event in the clear signal, wherein the first voltage level is outputted at the output of the DFF in place of the second voltage level in response to the clear event.

20. The method of claim 18 , further comprising:

detecting a trigger event in the data signal received by the DFF; and

in response to detection of the trigger event in the data signal:

controlling the DFF to sample the input signal at a first time; and

refreshing the function control signal to hold the second voltage level corresponding to the input signal sampled at the first time.