High voltage semiconductor device

1. A high voltage semiconductor device, comprising:

a P-type first body region and a N-type drift region formed in a semiconductor substrate;

a gate electrode formed over the P-type first body region and the N-type drift region;

an insulation layer formed over the N-type drift region and overlapped with the gate electrode;

a first isolation layer formed spaced apart from the insulation layer;

an N-type first well region formed in the N-type drift region, wherein the N-type first well region is in contact with both the insulation layer and the first isolation layer; and

an N-type second well region formed spaced apart from the N-type first well region and being in contact with the first isolation layer,

wherein a depth of the N-type second well region and a depth of the N-type first well region with respect to a top surface of the semiconductor substrate are substantially similar.

2. The high voltage semiconductor device of claim 1 , further comprising:

a P-type junction isolation region formed between the N-type first well region and the N-type second well region; and

an N-type junction isolation region formed adjacent to the P-type first body region, wherein the N-type junction isolation region has a depth deeper than a depth of the P-type junction isolation region.

3. The high voltage semiconductor device of claim 2 , wherein the P-type junction isolation region is disposed below the first isolation layer and having a depth deeper than a depth of the P-type first body region with respect to the top surface of the semiconductor substrate.

4. The high voltage semiconductor device of claim 1 , further comprising:

an N-type semiconductor region surrounding the N-type second well region, wherein a depth of the N-type semiconductor region and a depth of the N-type drift region are substantially similar.

5. The high voltage semiconductor device of claim 1 , further comprising:

an N-type first buried doping layer formed between the N-type drift region and the semiconductor substrate; and

an N-type second buried doping layer formed below the N-type second well region.

6. The high voltage semiconductor device of claim 1 , further comprising:

an N-type source region formed in the P-type first body region; and

an N-type drain region formed in the N-type first well region.

7. The high voltage semiconductor device of claim 6 , further comprising:

a P-type second body region formed adjacent to the N-type second well region; and

a P-type first doped region and a P-type second doped region both formed in the P-type second body region.

8. The high voltage semiconductor device of claim 7 , further comprising:

a metal interconnection formed on the first isolation layer, wherein the metal interconnection electrically connects the N-type drain region to the P-type first doped region.

9. A high voltage semiconductor device, comprising:

an N-type first buried doping layer and an N-type second buried doping layer formed in a semiconductor substrate;

an N-type first semiconductor region and an N-type second semiconductor region formed over the N-type first buried doping layer and the N-type second buried doping layer, respectively;

a metal interconnection electrically connecting the N-type first semiconductor region to the N-type second semiconductor region;

an N-type first well region and an N-type second well region formed in the N-type first semiconductor region and the N-type second semiconductor region, respectively;

a P-type first body region formed adjacent to the N-type first semiconductor region;

a P-type second body region formed in the N-type second semiconductor region;

an insulation layer formed over the N-type first semiconductor region; and

a first isolation layer formed over the N-type second semiconductor region, wherein the first isolation layer is in contact with the N-type first semiconductor region, the N-type second semiconductor region, the N-type first well region and the N-type second well region; and

a gate electrode formed overlapped with the insulation layer.

10. The high voltage semiconductor device of claim 9 , further comprising:

an N-type source region formed in the P-type first body region; and

an N-type drain region formed in the N-type first well region.

11. The high voltage semiconductor device of claim 9 , wherein a depth of the N-type first semiconductor region and a depth of the N-type second semiconductor region with respect to a top surface of the semiconductor substrate are substantially similar.

12. The high voltage semiconductor device of claim 9 , wherein a depth of the N-type first well region and a depth of the N-type second well region with respect to a top surface of the semiconductor substrate are substantially similar.

13. The high voltage semiconductor device of claim 9 , wherein a depth of the P-type first body region and a depth of the P-type second body region with respect to a top surface of the semiconductor substrate are substantially similar.

14. The high voltage semiconductor device of claim 9 , further comprising:

a P-type junction isolation region formed between the N-type first well region and the N-type second well region; and

an N-type junction isolation region formed adjacent to the P-type first body region, wherein the N-type junction isolation region has a depth deeper than a depth of the P-type junction isolation region.

15. The high voltage semiconductor device of claim 9 , wherein the N-type second well region is overlapped with the metal interconnection.