Offset gate contact
Offsetting or modulating the location of a gate between two transistors may achieve a lower power circuit and a higher speed circuit depending on the new location of the gate. In one example, a gate between a PFET transistor and an NFET transistor may be offset towards the PFET transistor to achieve a higher speed circuit than a conventional circuit with the gate located equal distance between the transistors. In another example, a gate between a PFET transistor and an NFET transistor may be offset towards the NFET transistor to achieve a lower power circuit than a conventional circuit with the gate located equal distance between the transistors.
1. A circuit comprising:
a first transistor coupled to a supply voltage, the first transistor comprising a gate region, a source contact, and a drain contact;
a second transistor coupled to a ground, the second transistor comprising a gate region, a source contact, and a drain contact; and
a first gate coupled to the first transistor and the second transistor at a first location, wherein the first location is offset from a center point between the first transistor and the second transistor.
2. The circuit of claim 1 , wherein the first location is closer to the first transistor than the second transistor.
3. The circuit of claim 1 , wherein the first location is closer to the second transistor than the first transistor.
4. The circuit of claim 1 , wherein the first transistor is a PFET and the second transistor is an NFET.
5. The circuit of claim 1 , wherein the first location is offset from the center point from 10 to 100 nm.
6. The circuit of claim 1 , further comprising a second gate coupled to the first transistor and the second transistor at a second location, wherein the second location is offset from the center point opposite the first location.
7. The circuit of claim 1 , wherein the first transistor is a PFET and the second transistor is an NFET and the circuit is an inverter circuit.
8. The circuit of claim 1 , wherein the first transistor is a pair of PFETs and the second transistor is a pair of NFETs and the circuit is a NOR circuit.
9. The circuit of claim 1 , wherein the circuit is incorporated into a device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, and a device in an automotive vehicle.
10. A circuit comprising:
a first means for amplifying coupled to a supply voltage, the first means for amplifying comprising a gate region, a source contact, and a drain contact;
a second means for amplifying coupled to a ground, the second means for amplifying comprising a gate region, a source contact, and a drain contact; and
a first gate coupled to the first means for amplifying and the second means for amplifying at a first location, wherein the first location is offset from a center point between the first means for amplifying and the second means for amplifying.
11. The circuit of claim 10 , wherein the first location is closer to the first means for amplifying than the second means for amplifying.
12. The circuit of claim 10 , wherein the first location is closer to the second means for amplifying than the first means for amplifying.
13. The circuit of claim 10 , wherein the first means for amplifying is a PFET and the second means for amplifying is an NFET.
14. The circuit of claim 10 , wherein the first location is offset from the center point from 10 to 100 nm.
15. The circuit of claim 10 , further comprising a second gate coupled to the first means for amplifying and the second means for amplifying at a second location, wherein the second location is offset from the center point opposite the first location.
16. The circuit of claim 10 , wherein the first means for amplifying is a PFET and the second means for amplifying is an NFET and the circuit is an inverter circuit.
17. The circuit of claim 10 , wherein the first means for amplifying is a pair of PFETs and the second means for amplifying is a pair of NFETs and the circuit is a NOR circuit.
18. The circuit of claim 10 , wherein the circuit is incorporated into a device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, and a device in an automotive vehicle.
19. A method for forming a circuit, the method comprising:
forming a gate region, a source contact, and a drain contact of a first transistor;
forming a gate region, a source contact, and a drain contact of a second transistor; and
forming a first gate coupled to the first transistor and the second transistor at a first location, wherein the first location is offset from a center point between the first transistor and the second transistor.
20. The method of claim 19 , further comprising forming a second gate coupled to the first transistor and the second transistor at a second location, wherein the second location is offset from the center point opposite the first location.